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GET /api/patches/92663/?format=api
{ "id": 92663, "url": "http://patches.dpdk.org/api/patches/92663/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210503152238.2437-26-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210503152238.2437-26-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210503152238.2437-26-pbhagavatula@marvell.com", "date": "2021-05-03T15:22:28", "name": "[v4,25/34] event/cnxk: allow adapters to resize inflights", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "fc70d0cd0a0bc664053cceb8afbf86bf92892af0", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210503152238.2437-26-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 16799, "url": "http://patches.dpdk.org/api/series/16799/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16799", "date": "2021-05-03T15:22:03", "name": "Marvell CNXK Event device Driver", "version": 4, "mbox": "http://patches.dpdk.org/series/16799/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/92663/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/92663/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 0231AA0562;\n\tMon, 3 May 2021 17:25:56 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B592C41199;\n\tMon, 3 May 2021 17:24:17 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 8F6694119E\n for <dev@dpdk.org>; Mon, 3 May 2021 17:24:16 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 143FApwB032456 for <dev@dpdk.org>; Mon, 3 May 2021 08:24:15 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 38agtfgv52-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Mon, 03 May 2021 08:24:15 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Mon, 3 May 2021 08:24:13 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Mon, 3 May 2021 08:24:14 -0700", "from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176])\n by maili.marvell.com (Postfix) with ESMTP id 52FF43F7041;\n Mon, 3 May 2021 08:24:12 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=5aR5D11nqtg+Mt4Fs3mJc1qUmLVBAW/lzvrDkeaGj24=;\n b=aFGjRpBMNzw2uh1ynIDMP/2y5p0589SX4LmDfW5cbaVUCcSStPv9NF232vIiR/FQRfxD\n X+3XcRDw6EFt9kMaTomnYdOx85mLqAZnUoNcphRkwSTWnapNAJTc05NL7K8HwfNdUq8E\n GaPwVUH4+G/TT0zzFryCB4tSMi9y8ew+JWtEsUZX/7WEJGz2v/d04O6Yk/zTcCO8bvKS\n 4wpce7vObythveS27Gv3EmcrkQPTtxy9DQzs66OLiFm8OXdS9ShCLVBKszuYjpWkc4aB\n ARVU73bsoroJMsPbq56mzN634bESoNiz6NgT96DVukNx6ox8nwzTeCyzlVr5std8WHV8 Tg==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>, \"Shijith\n Thotton\" <sthotton@marvell.com>", "CC": "<dev@dpdk.org>", "Date": "Mon, 3 May 2021 20:52:28 +0530", "Message-ID": "<20210503152238.2437-26-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210503152238.2437-1-pbhagavatula@marvell.com>", "References": "<20210430135336.2749-1-pbhagavatula@marvell.com>\n <20210503152238.2437-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "yE1vSrTxbZoF0AHL1DnwevwnGcmlZrqn", "X-Proofpoint-ORIG-GUID": "yE1vSrTxbZoF0AHL1DnwevwnGcmlZrqn", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761\n definitions=2021-05-03_10:2021-05-03,\n 2021-05-03 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 25/34] event/cnxk: allow adapters to resize\n inflights", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd internal SSO functions to allow event adapters to resize SSO buffers\nthat are used to hold in-flight events in DRAM.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\nSigned-off-by: Shijith Thotton <sthotton@marvell.com>\n---\n drivers/event/cnxk/cnxk_eventdev.c | 33 ++++++++++++\n drivers/event/cnxk/cnxk_eventdev.h | 7 +++\n drivers/event/cnxk/cnxk_eventdev_adptr.c | 67 ++++++++++++++++++++++++\n drivers/event/cnxk/cnxk_tim_evdev.c | 5 ++\n drivers/event/cnxk/meson.build | 1 +\n 5 files changed, 113 insertions(+)\n create mode 100644 drivers/event/cnxk/cnxk_eventdev_adptr.c", "diff": "diff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c\nindex 85bb12e00..7189ee3a7 100644\n--- a/drivers/event/cnxk/cnxk_eventdev.c\n+++ b/drivers/event/cnxk/cnxk_eventdev.c\n@@ -77,6 +77,9 @@ cnxk_sso_xaq_allocate(struct cnxk_sso_evdev *dev)\n \txaq_cnt = dev->nb_event_queues * CNXK_SSO_XAQ_CACHE_CNT;\n \tif (dev->xae_cnt)\n \t\txaq_cnt += dev->xae_cnt / dev->sso.xae_waes;\n+\telse if (dev->adptr_xae_cnt)\n+\t\txaq_cnt += (dev->adptr_xae_cnt / dev->sso.xae_waes) +\n+\t\t\t (CNXK_SSO_XAQ_SLACK * dev->nb_event_queues);\n \telse\n \t\txaq_cnt += (dev->sso.iue / dev->sso.xae_waes) +\n \t\t\t (CNXK_SSO_XAQ_SLACK * dev->nb_event_queues);\n@@ -125,6 +128,36 @@ cnxk_sso_xaq_allocate(struct cnxk_sso_evdev *dev)\n \treturn rc;\n }\n \n+int\n+cnxk_sso_xae_reconfigure(struct rte_eventdev *event_dev)\n+{\n+\tstruct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);\n+\tint rc = 0;\n+\n+\tif (event_dev->data->dev_started)\n+\t\tevent_dev->dev_ops->dev_stop(event_dev);\n+\n+\trc = roc_sso_hwgrp_release_xaq(&dev->sso, dev->nb_event_queues);\n+\tif (rc < 0) {\n+\t\tplt_err(\"Failed to release XAQ %d\", rc);\n+\t\treturn rc;\n+\t}\n+\n+\trte_mempool_free(dev->xaq_pool);\n+\tdev->xaq_pool = NULL;\n+\trc = cnxk_sso_xaq_allocate(dev);\n+\tif (rc < 0) {\n+\t\tplt_err(\"Failed to alloc XAQ %d\", rc);\n+\t\treturn rc;\n+\t}\n+\n+\trte_mb();\n+\tif (event_dev->data->dev_started)\n+\t\tevent_dev->dev_ops->dev_start(event_dev);\n+\n+\treturn 0;\n+}\n+\n int\n cnxk_setup_event_ports(const struct rte_eventdev *event_dev,\n \t\t cnxk_sso_init_hws_mem_t init_hws_fn,\ndiff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h\nindex 77835e463..668e51d62 100644\n--- a/drivers/event/cnxk/cnxk_eventdev.h\n+++ b/drivers/event/cnxk/cnxk_eventdev.h\n@@ -81,6 +81,10 @@ struct cnxk_sso_evdev {\n \tuint64_t nb_xaq_cfg;\n \trte_iova_t fc_iova;\n \tstruct rte_mempool *xaq_pool;\n+\tuint64_t adptr_xae_cnt;\n+\tuint16_t tim_adptr_ring_cnt;\n+\tuint16_t *timer_adptr_rings;\n+\tuint64_t *timer_adptr_sz;\n \t/* Dev args */\n \tuint32_t xae_cnt;\n \tuint8_t qos_queue_cnt;\n@@ -190,7 +194,10 @@ cnxk_sso_hws_get_cookie(void *ws)\n }\n \n /* Configuration functions */\n+int cnxk_sso_xae_reconfigure(struct rte_eventdev *event_dev);\n int cnxk_sso_xaq_allocate(struct cnxk_sso_evdev *dev);\n+void cnxk_sso_updt_xae_cnt(struct cnxk_sso_evdev *dev, void *data,\n+\t\t\t uint32_t event_type);\n \n /* Common ops API. */\n int cnxk_sso_init(struct rte_eventdev *event_dev);\ndiff --git a/drivers/event/cnxk/cnxk_eventdev_adptr.c b/drivers/event/cnxk/cnxk_eventdev_adptr.c\nnew file mode 100644\nindex 000000000..89a1d82c1\n--- /dev/null\n+++ b/drivers/event/cnxk/cnxk_eventdev_adptr.c\n@@ -0,0 +1,67 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"cnxk_eventdev.h\"\n+\n+void\n+cnxk_sso_updt_xae_cnt(struct cnxk_sso_evdev *dev, void *data,\n+\t\t uint32_t event_type)\n+{\n+\tint i;\n+\n+\tswitch (event_type) {\n+\tcase RTE_EVENT_TYPE_TIMER: {\n+\t\tstruct cnxk_tim_ring *timr = data;\n+\t\tuint16_t *old_ring_ptr;\n+\t\tuint64_t *old_sz_ptr;\n+\n+\t\tfor (i = 0; i < dev->tim_adptr_ring_cnt; i++) {\n+\t\t\tif (timr->ring_id != dev->timer_adptr_rings[i])\n+\t\t\t\tcontinue;\n+\t\t\tif (timr->nb_timers == dev->timer_adptr_sz[i])\n+\t\t\t\treturn;\n+\t\t\tdev->adptr_xae_cnt -= dev->timer_adptr_sz[i];\n+\t\t\tdev->adptr_xae_cnt += timr->nb_timers;\n+\t\t\tdev->timer_adptr_sz[i] = timr->nb_timers;\n+\n+\t\t\treturn;\n+\t\t}\n+\n+\t\tdev->tim_adptr_ring_cnt++;\n+\t\told_ring_ptr = dev->timer_adptr_rings;\n+\t\told_sz_ptr = dev->timer_adptr_sz;\n+\n+\t\tdev->timer_adptr_rings = rte_realloc(\n+\t\t\tdev->timer_adptr_rings,\n+\t\t\tsizeof(uint16_t) * dev->tim_adptr_ring_cnt, 0);\n+\t\tif (dev->timer_adptr_rings == NULL) {\n+\t\t\tdev->adptr_xae_cnt += timr->nb_timers;\n+\t\t\tdev->timer_adptr_rings = old_ring_ptr;\n+\t\t\tdev->tim_adptr_ring_cnt--;\n+\t\t\treturn;\n+\t\t}\n+\n+\t\tdev->timer_adptr_sz = rte_realloc(\n+\t\t\tdev->timer_adptr_sz,\n+\t\t\tsizeof(uint64_t) * dev->tim_adptr_ring_cnt, 0);\n+\n+\t\tif (dev->timer_adptr_sz == NULL) {\n+\t\t\tdev->adptr_xae_cnt += timr->nb_timers;\n+\t\t\tdev->timer_adptr_sz = old_sz_ptr;\n+\t\t\tdev->tim_adptr_ring_cnt--;\n+\t\t\treturn;\n+\t\t}\n+\n+\t\tdev->timer_adptr_rings[dev->tim_adptr_ring_cnt - 1] =\n+\t\t\ttimr->ring_id;\n+\t\tdev->timer_adptr_sz[dev->tim_adptr_ring_cnt - 1] =\n+\t\t\ttimr->nb_timers;\n+\n+\t\tdev->adptr_xae_cnt += timr->nb_timers;\n+\t\tbreak;\n+\t}\n+\tdefault:\n+\t\tbreak;\n+\t}\n+}\ndiff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c\nindex d93b37e4f..1eb39a789 100644\n--- a/drivers/event/cnxk/cnxk_tim_evdev.c\n+++ b/drivers/event/cnxk/cnxk_tim_evdev.c\n@@ -161,6 +161,11 @@ cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr)\n \tplt_write64((uint64_t)tim_ring->bkt, tim_ring->base + TIM_LF_RING_BASE);\n \tplt_write64(tim_ring->aura, tim_ring->base + TIM_LF_RING_AURA);\n \n+\t/* Update SSO xae count. */\n+\tcnxk_sso_updt_xae_cnt(cnxk_sso_pmd_priv(dev->event_dev), tim_ring,\n+\t\t\t RTE_EVENT_TYPE_TIMER);\n+\tcnxk_sso_xae_reconfigure(dev->event_dev);\n+\n \tplt_tim_dbg(\n \t\t\"Total memory used %\" PRIu64 \"MB\\n\",\n \t\t(uint64_t)(((tim_ring->nb_chunks * tim_ring->chunk_sz) +\ndiff --git a/drivers/event/cnxk/meson.build b/drivers/event/cnxk/meson.build\nindex ce8764eda..bd52cbc68 100644\n--- a/drivers/event/cnxk/meson.build\n+++ b/drivers/event/cnxk/meson.build\n@@ -12,6 +12,7 @@ sources = files('cn10k_worker.c',\n 'cn10k_eventdev.c',\n 'cn9k_worker.c',\n 'cn9k_eventdev.c',\n+ 'cnxk_eventdev_adptr.c',\n 'cnxk_eventdev.c',\n 'cnxk_eventdev_selftest.c',\n 'cnxk_eventdev_stats.c',\n", "prefixes": [ "v4", "25/34" ] }