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GET /api/patches/92662/?format=api
{ "id": 92662, "url": "http://patches.dpdk.org/api/patches/92662/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210503152238.2437-25-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210503152238.2437-25-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210503152238.2437-25-pbhagavatula@marvell.com", "date": "2021-05-03T15:22:27", "name": "[v4,24/34] event/cnxk: add devargs to disable NPA", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "5f176f9f35a490e5e2f5cb04d321537bbb838f6b", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210503152238.2437-25-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 16799, "url": "http://patches.dpdk.org/api/series/16799/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16799", "date": "2021-05-03T15:22:03", "name": "Marvell CNXK Event device Driver", "version": 4, "mbox": "http://patches.dpdk.org/series/16799/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/92662/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/92662/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id EA13AA0562;\n\tMon, 3 May 2021 17:25:49 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7B2A14119B;\n\tMon, 3 May 2021 17:24:14 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id EBD0641195\n for <dev@dpdk.org>; Mon, 3 May 2021 17:24:12 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 143FB9lX032612 for <dev@dpdk.org>; Mon, 3 May 2021 08:24:12 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com with ESMTP id 38agtfgv4t-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Mon, 03 May 2021 08:24:12 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Mon, 3 May 2021 08:24:10 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Mon, 3 May 2021 08:24:10 -0700", "from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176])\n by maili.marvell.com (Postfix) with ESMTP id EDDED3F703F;\n Mon, 3 May 2021 08:24:08 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=5re+N9i/eSpFPK3PcCnvmwyULUaV7SBo3xeCw4Ijakk=;\n b=ByTbS0Zuog/vY1QJbwtuiTCvDM4qQbRANXY7FXxmR8olwCa3CdfP7HjqWxA2p3rBHx8G\n x4Ip4KDv0YMLfHuvkl23Z1OL2HqsXp9nC0zytu+mTyQXlswLU46/4KIaumEWIUZJwT5i\n HuX5Ewycw0SWtyO/x6EofXFODCe4AkLPsGT7A58+FfM41pKSknziTbze5ooVSEB2oKam\n qiF3JbUp6z9YpGvDeJtpPOFVzK/H2Y2BdCZlMD2/4XrlqvAOHugWrG8KXv9GQpQsnLO5\n krFB6e03SigJ+P10T3QE8qqJIpiJUNa8e1MxaGMDg8EJH9Nhtb0tfrR3Tr9iEkx6hjGK kg==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>, \"Shijith\n Thotton\" <sthotton@marvell.com>", "CC": "<dev@dpdk.org>", "Date": "Mon, 3 May 2021 20:52:27 +0530", "Message-ID": "<20210503152238.2437-25-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210503152238.2437-1-pbhagavatula@marvell.com>", "References": "<20210430135336.2749-1-pbhagavatula@marvell.com>\n <20210503152238.2437-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "8BMqPX2NCCncz5yk-OyoegNlIei5SbqQ", "X-Proofpoint-ORIG-GUID": "8BMqPX2NCCncz5yk-OyoegNlIei5SbqQ", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761\n definitions=2021-05-03_10:2021-05-03,\n 2021-05-03 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 24/34] event/cnxk: add devargs to disable NPA", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nIf the chunks are allocated from NPA then TIM can automatically free\nthem when traversing the list of chunks.\nAdd devargs to disable NPA and use software mempool to manage chunks.\n\nExample:\n\t--dev \"0002:0e:00.0,tim_disable_npa=1\"\n\nSigned-off-by: Shijith Thotton <sthotton@marvell.com>\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n doc/guides/eventdevs/cnxk.rst | 10 ++++\n drivers/event/cnxk/cn10k_eventdev.c | 3 +-\n drivers/event/cnxk/cn9k_eventdev.c | 3 +-\n drivers/event/cnxk/cnxk_eventdev.h | 9 +++\n drivers/event/cnxk/cnxk_tim_evdev.c | 86 +++++++++++++++++++++--------\n drivers/event/cnxk/cnxk_tim_evdev.h | 5 ++\n 6 files changed, 92 insertions(+), 24 deletions(-)", "diff": "diff --git a/doc/guides/eventdevs/cnxk.rst b/doc/guides/eventdevs/cnxk.rst\nindex e6f81f8b1..c2d6ed2fb 100644\n--- a/doc/guides/eventdevs/cnxk.rst\n+++ b/doc/guides/eventdevs/cnxk.rst\n@@ -93,6 +93,16 @@ Runtime Config Options\n \n -a 0002:0e:00.0,qos=[1-50-50-50]\n \n+- ``TIM disable NPA``\n+\n+ By default chunks are allocated from NPA then TIM can automatically free\n+ them when traversing the list of chunks. The ``tim_disable_npa`` devargs\n+ parameter disables NPA and uses software mempool to manage chunks\n+\n+ For example::\n+\n+ -a 0002:0e:00.0,tim_disable_npa=1\n+\n Debugging Options\n -----------------\n \ndiff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c\nindex 0981085e8..a2ef1fa73 100644\n--- a/drivers/event/cnxk/cn10k_eventdev.c\n+++ b/drivers/event/cnxk/cn10k_eventdev.c\n@@ -502,4 +502,5 @@ RTE_PMD_REGISTER_PCI_TABLE(event_cn10k, cn10k_pci_sso_map);\n RTE_PMD_REGISTER_KMOD_DEP(event_cn10k, \"vfio-pci\");\n RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT \"=<int>\"\n \t\t\t CNXK_SSO_GGRP_QOS \"=<string>\"\n-\t\t\t CN10K_SSO_GW_MODE \"=<int>\");\n+\t\t\t CN10K_SSO_GW_MODE \"=<int>\"\n+\t\t\t CNXK_TIM_DISABLE_NPA \"=1\");\ndiff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c\nindex d9882ebb9..3a0caa009 100644\n--- a/drivers/event/cnxk/cn9k_eventdev.c\n+++ b/drivers/event/cnxk/cn9k_eventdev.c\n@@ -571,4 +571,5 @@ RTE_PMD_REGISTER_PCI_TABLE(event_cn9k, cn9k_pci_sso_map);\n RTE_PMD_REGISTER_KMOD_DEP(event_cn9k, \"vfio-pci\");\n RTE_PMD_REGISTER_PARAM_STRING(event_cn9k, CNXK_SSO_XAE_CNT \"=<int>\"\n \t\t\t CNXK_SSO_GGRP_QOS \"=<string>\"\n-\t\t\t CN9K_SSO_SINGLE_WS \"=1\");\n+\t\t\t CN9K_SSO_SINGLE_WS \"=1\"\n+\t\t\t CNXK_TIM_DISABLE_NPA \"=1\");\ndiff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h\nindex 1c61063c9..77835e463 100644\n--- a/drivers/event/cnxk/cnxk_eventdev.h\n+++ b/drivers/event/cnxk/cnxk_eventdev.h\n@@ -159,6 +159,15 @@ struct cnxk_sso_hws_cookie {\n \tbool configured;\n } __rte_cache_aligned;\n \n+static inline int\n+parse_kvargs_flag(const char *key, const char *value, void *opaque)\n+{\n+\tRTE_SET_USED(key);\n+\n+\t*(uint8_t *)opaque = !!atoi(value);\n+\treturn 0;\n+}\n+\n static inline int\n parse_kvargs_value(const char *key, const char *value, void *opaque)\n {\ndiff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c\nindex 655540a72..d93b37e4f 100644\n--- a/drivers/event/cnxk/cnxk_tim_evdev.c\n+++ b/drivers/event/cnxk/cnxk_tim_evdev.c\n@@ -31,30 +31,43 @@ cnxk_tim_chnk_pool_create(struct cnxk_tim_ring *tim_ring,\n \t\tcache_sz = RTE_MEMPOOL_CACHE_MAX_SIZE;\n \tcache_sz = cache_sz != 0 ? cache_sz : 2;\n \ttim_ring->nb_chunks += (cache_sz * rte_lcore_count());\n-\ttim_ring->chunk_pool = rte_mempool_create_empty(\n-\t\tpool_name, tim_ring->nb_chunks, tim_ring->chunk_sz, cache_sz, 0,\n-\t\trte_socket_id(), mp_flags);\n-\n-\tif (tim_ring->chunk_pool == NULL) {\n-\t\tplt_err(\"Unable to create chunkpool.\");\n-\t\treturn -ENOMEM;\n-\t}\n+\tif (!tim_ring->disable_npa) {\n+\t\ttim_ring->chunk_pool = rte_mempool_create_empty(\n+\t\t\tpool_name, tim_ring->nb_chunks, tim_ring->chunk_sz,\n+\t\t\tcache_sz, 0, rte_socket_id(), mp_flags);\n+\n+\t\tif (tim_ring->chunk_pool == NULL) {\n+\t\t\tplt_err(\"Unable to create chunkpool.\");\n+\t\t\treturn -ENOMEM;\n+\t\t}\n \n-\trc = rte_mempool_set_ops_byname(tim_ring->chunk_pool,\n-\t\t\t\t\trte_mbuf_platform_mempool_ops(), NULL);\n-\tif (rc < 0) {\n-\t\tplt_err(\"Unable to set chunkpool ops\");\n-\t\tgoto free;\n-\t}\n+\t\trc = rte_mempool_set_ops_byname(tim_ring->chunk_pool,\n+\t\t\t\t\t\trte_mbuf_platform_mempool_ops(),\n+\t\t\t\t\t\tNULL);\n+\t\tif (rc < 0) {\n+\t\t\tplt_err(\"Unable to set chunkpool ops\");\n+\t\t\tgoto free;\n+\t\t}\n \n-\trc = rte_mempool_populate_default(tim_ring->chunk_pool);\n-\tif (rc < 0) {\n-\t\tplt_err(\"Unable to set populate chunkpool.\");\n-\t\tgoto free;\n+\t\trc = rte_mempool_populate_default(tim_ring->chunk_pool);\n+\t\tif (rc < 0) {\n+\t\t\tplt_err(\"Unable to set populate chunkpool.\");\n+\t\t\tgoto free;\n+\t\t}\n+\t\ttim_ring->aura = roc_npa_aura_handle_to_aura(\n+\t\t\ttim_ring->chunk_pool->pool_id);\n+\t\ttim_ring->ena_dfb = 0;\n+\t} else {\n+\t\ttim_ring->chunk_pool = rte_mempool_create(\n+\t\t\tpool_name, tim_ring->nb_chunks, tim_ring->chunk_sz,\n+\t\t\tcache_sz, 0, NULL, NULL, NULL, NULL, rte_socket_id(),\n+\t\t\tmp_flags);\n+\t\tif (tim_ring->chunk_pool == NULL) {\n+\t\t\tplt_err(\"Unable to create chunkpool.\");\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t\ttim_ring->ena_dfb = 1;\n \t}\n-\ttim_ring->aura =\n-\t\troc_npa_aura_handle_to_aura(tim_ring->chunk_pool->pool_id);\n-\ttim_ring->ena_dfb = 0;\n \n \treturn 0;\n \n@@ -110,8 +123,17 @@ cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr)\n \ttim_ring->nb_bkts = (tim_ring->max_tout / tim_ring->tck_nsec);\n \ttim_ring->nb_timers = rcfg->nb_timers;\n \ttim_ring->chunk_sz = dev->chunk_sz;\n+\ttim_ring->disable_npa = dev->disable_npa;\n+\n+\tif (tim_ring->disable_npa) {\n+\t\ttim_ring->nb_chunks =\n+\t\t\ttim_ring->nb_timers /\n+\t\t\tCNXK_TIM_NB_CHUNK_SLOTS(tim_ring->chunk_sz);\n+\t\ttim_ring->nb_chunks = tim_ring->nb_chunks * tim_ring->nb_bkts;\n+\t} else {\n+\t\ttim_ring->nb_chunks = tim_ring->nb_timers;\n+\t}\n \n-\ttim_ring->nb_chunks = tim_ring->nb_timers;\n \ttim_ring->nb_chunk_slots = CNXK_TIM_NB_CHUNK_SLOTS(tim_ring->chunk_sz);\n \t/* Create buckets. */\n \ttim_ring->bkt =\n@@ -199,6 +221,24 @@ cnxk_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags,\n \treturn 0;\n }\n \n+static void\n+cnxk_tim_parse_devargs(struct rte_devargs *devargs, struct cnxk_tim_evdev *dev)\n+{\n+\tstruct rte_kvargs *kvlist;\n+\n+\tif (devargs == NULL)\n+\t\treturn;\n+\n+\tkvlist = rte_kvargs_parse(devargs->args, NULL);\n+\tif (kvlist == NULL)\n+\t\treturn;\n+\n+\trte_kvargs_process(kvlist, CNXK_TIM_DISABLE_NPA, &parse_kvargs_flag,\n+\t\t\t &dev->disable_npa);\n+\n+\trte_kvargs_free(kvlist);\n+}\n+\n void\n cnxk_tim_init(struct roc_sso *sso)\n {\n@@ -217,6 +257,8 @@ cnxk_tim_init(struct roc_sso *sso)\n \t}\n \tdev = mz->addr;\n \n+\tcnxk_tim_parse_devargs(sso->pci_dev->device.devargs, dev);\n+\n \tdev->tim.roc_sso = sso;\n \trc = roc_tim_init(&dev->tim);\n \tif (rc < 0) {\ndiff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h\nindex 2335707cd..4896ed67a 100644\n--- a/drivers/event/cnxk/cnxk_tim_evdev.h\n+++ b/drivers/event/cnxk/cnxk_tim_evdev.h\n@@ -33,11 +33,15 @@\n \n #define CN9K_TIM_MIN_TMO_TKS (256)\n \n+#define CNXK_TIM_DISABLE_NPA \"tim_disable_npa\"\n+\n struct cnxk_tim_evdev {\n \tstruct roc_tim tim;\n \tstruct rte_eventdev *event_dev;\n \tuint16_t nb_rings;\n \tuint32_t chunk_sz;\n+\t/* Dev args */\n+\tuint8_t disable_npa;\n };\n \n enum cnxk_tim_clk_src {\n@@ -75,6 +79,7 @@ struct cnxk_tim_ring {\n \tstruct rte_mempool *chunk_pool;\n \tuint64_t arm_cnt;\n \tuint8_t prod_type_sp;\n+\tuint8_t disable_npa;\n \tuint8_t ena_dfb;\n \tuint16_t ring_id;\n \tuint32_t aura;\n", "prefixes": [ "v4", "24/34" ] }