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GET /api/patches/92659/?format=api
http://patches.dpdk.org/api/patches/92659/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210503152238.2437-22-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210503152238.2437-22-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210503152238.2437-22-pbhagavatula@marvell.com", "date": "2021-05-03T15:22:24", "name": "[v4,21/34] event/cnxk: support event timer", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "4fa83f0871987d5048fa89d33a7d66f02f947889", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210503152238.2437-22-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 16799, "url": "http://patches.dpdk.org/api/series/16799/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16799", "date": "2021-05-03T15:22:03", "name": "Marvell CNXK Event device Driver", "version": 4, "mbox": "http://patches.dpdk.org/series/16799/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/92659/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/92659/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1A761A0562;\n\tMon, 3 May 2021 17:25:29 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 599564114A;\n\tMon, 3 May 2021 17:24:05 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 798C04118C\n for <dev@dpdk.org>; Mon, 3 May 2021 17:24:03 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 143FB9lV032612; Mon, 3 May 2021 08:24:02 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com with ESMTP id 38agtfgv42-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Mon, 03 May 2021 08:24:02 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Mon, 3 May 2021 08:24:01 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Mon, 3 May 2021 08:24:00 -0700", "from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176])\n by maili.marvell.com (Postfix) with ESMTP id 6F4FF3F703F;\n Mon, 3 May 2021 08:23:58 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=yEQuOodInjHetHE6+MkCKh9GK+K6E39TlXbX80HQARQ=;\n b=JTJP/BlVRAalL57G8+SWWMym7AhPTg2RUUGcAi1QAbAAmIp9OlRdRr+HnIATR/gqNhfF\n Golk+GqoxSxpY9FI8Vya4rVQQ79rCli+AVKC7kdQ7Zotbh2lvBxg3SKJOYqXgvtNRZ3o\n pJ6iYNzfsgxWP2Oovwy1Xa58/olLmoaFg1vDQT8aPJ/yDgya+SrTHHnSesVuZqEzQoIf\n fOd6k4pZc3Nk8e+6+DPv8M3832tayx4UMLCJXYkCToF5OfckRxjBKqGhWlwX8HHVrhMK\n 3hRSdLBXLPqf53A4K9kslt2aR9wKhPMZptiwz2hEExYdRtck13aTcHTDadBNBFLIDBFU wg==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>, \"Shijith\n Thotton\" <sthotton@marvell.com>,\n Anatoly Burakov <anatoly.burakov@intel.com>", "CC": "<dev@dpdk.org>", "Date": "Mon, 3 May 2021 20:52:24 +0530", "Message-ID": "<20210503152238.2437-22-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210503152238.2437-1-pbhagavatula@marvell.com>", "References": "<20210430135336.2749-1-pbhagavatula@marvell.com>\n <20210503152238.2437-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "s7MUbFBqKbJZndP8MnH2FKrITwy4VUsf", "X-Proofpoint-ORIG-GUID": "s7MUbFBqKbJZndP8MnH2FKrITwy4VUsf", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761\n definitions=2021-05-03_10:2021-05-03,\n 2021-05-03 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 21/34] event/cnxk: support event timer", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Shijith Thotton <sthotton@marvell.com>\n\nAdd event timer adapter a.k.a TIM initialization on SSO probe.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\nSigned-off-by: Shijith Thotton <sthotton@marvell.com>\n---\n doc/guides/eventdevs/cnxk.rst | 6 ++++\n drivers/event/cnxk/cnxk_eventdev.c | 3 ++\n drivers/event/cnxk/cnxk_eventdev.h | 2 ++\n drivers/event/cnxk/cnxk_tim_evdev.c | 47 +++++++++++++++++++++++++++++\n drivers/event/cnxk/cnxk_tim_evdev.h | 44 +++++++++++++++++++++++++++\n drivers/event/cnxk/meson.build | 1 +\n 6 files changed, 103 insertions(+)\n create mode 100644 drivers/event/cnxk/cnxk_tim_evdev.c\n create mode 100644 drivers/event/cnxk/cnxk_tim_evdev.h", "diff": "diff --git a/doc/guides/eventdevs/cnxk.rst b/doc/guides/eventdevs/cnxk.rst\nindex f48452982..e6f81f8b1 100644\n--- a/doc/guides/eventdevs/cnxk.rst\n+++ b/doc/guides/eventdevs/cnxk.rst\n@@ -35,6 +35,10 @@ Features of the OCTEON cnxk SSO PMD are:\n - Open system with configurable amount of outstanding events limited only by\n DRAM\n - HW accelerated dequeue timeout support to enable power management\n+- HW managed event timers support through TIM, with high precision and\n+ time granularity of 2.5us on CN9K and 1us on CN10K.\n+- Up to 256 TIM rings a.k.a event timer adapters.\n+- Up to 8 rings traversed in parallel.\n \n Prerequisites and Compilation procedure\n ---------------------------------------\n@@ -101,3 +105,5 @@ Debugging Options\n +===+============+=======================================================+\n | 1 | SSO | --log-level='pmd\\.event\\.cnxk,8' |\n +---+------------+-------------------------------------------------------+\n+ | 2 | TIM | --log-level='pmd\\.event\\.cnxk\\.timer,8' |\n+ +---+------------+-------------------------------------------------------+\ndiff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c\nindex 0f084176c..85bb12e00 100644\n--- a/drivers/event/cnxk/cnxk_eventdev.c\n+++ b/drivers/event/cnxk/cnxk_eventdev.c\n@@ -582,6 +582,8 @@ cnxk_sso_init(struct rte_eventdev *event_dev)\n \tdev->nb_event_queues = 0;\n \tdev->nb_event_ports = 0;\n \n+\tcnxk_tim_init(&dev->sso);\n+\n \treturn 0;\n \n error:\n@@ -598,6 +600,7 @@ cnxk_sso_fini(struct rte_eventdev *event_dev)\n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n \t\treturn 0;\n \n+\tcnxk_tim_fini();\n \troc_sso_rsrc_fini(&dev->sso);\n \troc_sso_dev_fini(&dev->sso);\n \ndiff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h\nindex abe36f21f..1c61063c9 100644\n--- a/drivers/event/cnxk/cnxk_eventdev.h\n+++ b/drivers/event/cnxk/cnxk_eventdev.h\n@@ -14,6 +14,8 @@\n \n #include \"roc_api.h\"\n \n+#include \"cnxk_tim_evdev.h\"\n+\n #define CNXK_SSO_XAE_CNT \"xae_cnt\"\n #define CNXK_SSO_GGRP_QOS \"qos\"\n #define CN9K_SSO_SINGLE_WS \"single_ws\"\ndiff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c\nnew file mode 100644\nindex 000000000..46461b885\n--- /dev/null\n+++ b/drivers/event/cnxk/cnxk_tim_evdev.c\n@@ -0,0 +1,47 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"cnxk_eventdev.h\"\n+#include \"cnxk_tim_evdev.h\"\n+\n+void\n+cnxk_tim_init(struct roc_sso *sso)\n+{\n+\tconst struct rte_memzone *mz;\n+\tstruct cnxk_tim_evdev *dev;\n+\tint rc;\n+\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n+\t\treturn;\n+\n+\tmz = rte_memzone_reserve(RTE_STR(CNXK_TIM_EVDEV_NAME),\n+\t\t\t\t sizeof(struct cnxk_tim_evdev), 0, 0);\n+\tif (mz == NULL) {\n+\t\tplt_tim_dbg(\"Unable to allocate memory for TIM Event device\");\n+\t\treturn;\n+\t}\n+\tdev = mz->addr;\n+\n+\tdev->tim.roc_sso = sso;\n+\trc = roc_tim_init(&dev->tim);\n+\tif (rc < 0) {\n+\t\tplt_err(\"Failed to initialize roc tim resources\");\n+\t\trte_memzone_free(mz);\n+\t\treturn;\n+\t}\n+\tdev->nb_rings = rc;\n+\tdev->chunk_sz = CNXK_TIM_RING_DEF_CHUNK_SZ;\n+}\n+\n+void\n+cnxk_tim_fini(void)\n+{\n+\tstruct cnxk_tim_evdev *dev = tim_priv_get();\n+\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n+\t\treturn;\n+\n+\troc_tim_fini(&dev->tim);\n+\trte_memzone_free(rte_memzone_lookup(RTE_STR(CNXK_TIM_EVDEV_NAME)));\n+}\ndiff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h\nnew file mode 100644\nindex 000000000..5ddc94ed4\n--- /dev/null\n+++ b/drivers/event/cnxk/cnxk_tim_evdev.h\n@@ -0,0 +1,44 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#ifndef __CNXK_TIM_EVDEV_H__\n+#define __CNXK_TIM_EVDEV_H__\n+\n+#include <stddef.h>\n+#include <stdint.h>\n+#include <stdlib.h>\n+#include <string.h>\n+\n+#include <eventdev_pmd_pci.h>\n+#include <rte_event_timer_adapter.h>\n+#include <rte_memzone.h>\n+\n+#include \"roc_api.h\"\n+\n+#define CNXK_TIM_EVDEV_NAME\t cnxk_tim_eventdev\n+#define CNXK_TIM_RING_DEF_CHUNK_SZ (4096)\n+\n+struct cnxk_tim_evdev {\n+\tstruct roc_tim tim;\n+\tstruct rte_eventdev *event_dev;\n+\tuint16_t nb_rings;\n+\tuint32_t chunk_sz;\n+};\n+\n+static inline struct cnxk_tim_evdev *\n+tim_priv_get(void)\n+{\n+\tconst struct rte_memzone *mz;\n+\n+\tmz = rte_memzone_lookup(RTE_STR(CNXK_TIM_EVDEV_NAME));\n+\tif (mz == NULL)\n+\t\treturn NULL;\n+\n+\treturn mz->addr;\n+}\n+\n+void cnxk_tim_init(struct roc_sso *sso);\n+void cnxk_tim_fini(void);\n+\n+#endif /* __CNXK_TIM_EVDEV_H__ */\ndiff --git a/drivers/event/cnxk/meson.build b/drivers/event/cnxk/meson.build\nindex 5b215b73f..ce8764eda 100644\n--- a/drivers/event/cnxk/meson.build\n+++ b/drivers/event/cnxk/meson.build\n@@ -15,6 +15,7 @@ sources = files('cn10k_worker.c',\n 'cnxk_eventdev.c',\n 'cnxk_eventdev_selftest.c',\n 'cnxk_eventdev_stats.c',\n+ 'cnxk_tim_evdev.c',\n )\n \n deps += ['bus_pci', 'common_cnxk']\n", "prefixes": [ "v4", "21/34" ] }{ "id": 92659, "url": "