Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/92643/?format=api
{ "id": 92643, "url": "http://patches.dpdk.org/api/patches/92643/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210503152238.2437-6-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210503152238.2437-6-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210503152238.2437-6-pbhagavatula@marvell.com", "date": "2021-05-03T15:22:08", "name": "[v4,05/34] event/cnxk: add common configuration validation", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "1496770067d4a11fa4060d02a5e08a138fe4965f", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210503152238.2437-6-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 16799, "url": "http://patches.dpdk.org/api/series/16799/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16799", "date": "2021-05-03T15:22:03", "name": "Marvell CNXK Event device Driver", "version": 4, "mbox": "http://patches.dpdk.org/series/16799/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/92643/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/92643/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id BA70BA0562;\n\tMon, 3 May 2021 17:23:23 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 500DC4112D;\n\tMon, 3 May 2021 17:23:07 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 06FAE4112D\n for <dev@dpdk.org>; Mon, 3 May 2021 17:23:05 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 143FA9sp032495 for <dev@dpdk.org>; Mon, 3 May 2021 08:23:05 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 38ad05hee1-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Mon, 03 May 2021 08:23:05 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Mon, 3 May 2021 08:23:03 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Mon, 3 May 2021 08:23:03 -0700", "from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176])\n by maili.marvell.com (Postfix) with ESMTP id 7B06C3F7040;\n Mon, 3 May 2021 08:23:01 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=InuxCcz6qd7A7MiGlNB8Uit2E73/EZskGRyZV6uD3fU=;\n b=U4rqkMHAsJAgoADQRBFGQpEvfCkhMLEPLNPs5wjzco6d/EYiOsKUEBRGcQlZd3qZzxkX\n 4+O5R7ojTKIZSthvoJBfi2u4FNlZ6OAWumDTk2ZwPYu+LA9iJTlh4T8Fdh4HQWBHN3uP\n S7LY+YO5/Q2j5m11jzLmzsW8VJ0eKrxEGRPxHVnSQGJBB+QoPUQjHdUNJdubviJQrIlj\n yXf3G+2dA9oXE0afThOnthTJNQfZJ7bBBvNHSP+lt5461Iz/4hYVfIrQS1hk9Dz1xKlA\n P4ExjUbabtSUDmU0UvaefrB9fwfNlPdFOX1QlL8EarbQ5fpmSghcsX1+xJp59HKqAr6b dg==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>, \"Shijith\n Thotton\" <sthotton@marvell.com>", "CC": "<dev@dpdk.org>", "Date": "Mon, 3 May 2021 20:52:08 +0530", "Message-ID": "<20210503152238.2437-6-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210503152238.2437-1-pbhagavatula@marvell.com>", "References": "<20210430135336.2749-1-pbhagavatula@marvell.com>\n <20210503152238.2437-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "UjPFOnBKp0URJF9w5nKe2V2_zMk5ey1t", "X-Proofpoint-ORIG-GUID": "UjPFOnBKp0URJF9w5nKe2V2_zMk5ey1t", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761\n definitions=2021-05-03_10:2021-05-03,\n 2021-05-03 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 05/34] event/cnxk: add common configuration\n validation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd configuration validation, port and queue configuration\nfunctions.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\nSigned-off-by: Shijith Thotton <sthotton@marvell.com>\n---\n drivers/event/cnxk/cnxk_eventdev.c | 70 ++++++++++++++++++++++++++++++\n drivers/event/cnxk/cnxk_eventdev.h | 6 +++\n 2 files changed, 76 insertions(+)", "diff": "diff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c\nindex 3a7053af6..3eab1ed29 100644\n--- a/drivers/event/cnxk/cnxk_eventdev.c\n+++ b/drivers/event/cnxk/cnxk_eventdev.c\n@@ -28,6 +28,76 @@ cnxk_sso_info_get(struct cnxk_sso_evdev *dev,\n \t\t\t\t RTE_EVENT_DEV_CAP_CARRY_FLOW_ID;\n }\n \n+int\n+cnxk_sso_dev_validate(const struct rte_eventdev *event_dev)\n+{\n+\tstruct rte_event_dev_config *conf = &event_dev->data->dev_conf;\n+\tstruct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);\n+\tuint32_t deq_tmo_ns;\n+\n+\tdeq_tmo_ns = conf->dequeue_timeout_ns;\n+\n+\tif (deq_tmo_ns == 0)\n+\t\tdeq_tmo_ns = dev->min_dequeue_timeout_ns;\n+\tif (deq_tmo_ns < dev->min_dequeue_timeout_ns ||\n+\t deq_tmo_ns > dev->max_dequeue_timeout_ns) {\n+\t\tplt_err(\"Unsupported dequeue timeout requested\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (conf->event_dev_cfg & RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT)\n+\t\tdev->is_timeout_deq = 1;\n+\n+\tdev->deq_tmo_ns = deq_tmo_ns;\n+\n+\tif (!conf->nb_event_queues || !conf->nb_event_ports ||\n+\t conf->nb_event_ports > dev->max_event_ports ||\n+\t conf->nb_event_queues > dev->max_event_queues) {\n+\t\tplt_err(\"Unsupported event queues/ports requested\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (conf->nb_event_port_dequeue_depth > 1) {\n+\t\tplt_err(\"Unsupported event port deq depth requested\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (conf->nb_event_port_enqueue_depth > 1) {\n+\t\tplt_err(\"Unsupported event port enq depth requested\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tdev->nb_event_queues = conf->nb_event_queues;\n+\tdev->nb_event_ports = conf->nb_event_ports;\n+\n+\treturn 0;\n+}\n+\n+void\n+cnxk_sso_queue_def_conf(struct rte_eventdev *event_dev, uint8_t queue_id,\n+\t\t\tstruct rte_event_queue_conf *queue_conf)\n+{\n+\tRTE_SET_USED(event_dev);\n+\tRTE_SET_USED(queue_id);\n+\n+\tqueue_conf->nb_atomic_flows = (1ULL << 20);\n+\tqueue_conf->nb_atomic_order_sequences = (1ULL << 20);\n+\tqueue_conf->event_queue_cfg = RTE_EVENT_QUEUE_CFG_ALL_TYPES;\n+\tqueue_conf->priority = RTE_EVENT_DEV_PRIORITY_NORMAL;\n+}\n+\n+void\n+cnxk_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id,\n+\t\t struct rte_event_port_conf *port_conf)\n+{\n+\tstruct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);\n+\n+\tRTE_SET_USED(port_id);\n+\tport_conf->new_event_threshold = dev->max_num_events;\n+\tport_conf->dequeue_depth = 1;\n+\tport_conf->enqueue_depth = 1;\n+}\n+\n int\n cnxk_sso_init(struct rte_eventdev *event_dev)\n {\ndiff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h\nindex 6bdf0b347..59d96a08f 100644\n--- a/drivers/event/cnxk/cnxk_eventdev.h\n+++ b/drivers/event/cnxk/cnxk_eventdev.h\n@@ -22,6 +22,7 @@ struct cnxk_sso_evdev {\n \tuint8_t is_timeout_deq;\n \tuint8_t nb_event_queues;\n \tuint8_t nb_event_ports;\n+\tuint32_t deq_tmo_ns;\n \tuint32_t min_dequeue_timeout_ns;\n \tuint32_t max_dequeue_timeout_ns;\n \tint32_t max_num_events;\n@@ -41,5 +42,10 @@ int cnxk_sso_fini(struct rte_eventdev *event_dev);\n int cnxk_sso_remove(struct rte_pci_device *pci_dev);\n void cnxk_sso_info_get(struct cnxk_sso_evdev *dev,\n \t\t struct rte_event_dev_info *dev_info);\n+int cnxk_sso_dev_validate(const struct rte_eventdev *event_dev);\n+void cnxk_sso_queue_def_conf(struct rte_eventdev *event_dev, uint8_t queue_id,\n+\t\t\t struct rte_event_queue_conf *queue_conf);\n+void cnxk_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id,\n+\t\t\t struct rte_event_port_conf *port_conf);\n \n #endif /* __CNXK_EVENTDEV_H__ */\n", "prefixes": [ "v4", "05/34" ] }