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GET /api/patches/92277/?format=api
{ "id": 92277, "url": "http://patches.dpdk.org/api/patches/92277/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210427153811.11554-13-bingz@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210427153811.11554-13-bingz@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210427153811.11554-13-bingz@nvidia.com", "date": "2021-04-27T15:38:06", "name": "[12/17] net/mlx5: add translation of CT item", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "5a652f53f909156b42a350f3ebd7b7b37a98aa38", "submitter": { "id": 1976, "url": "http://patches.dpdk.org/api/people/1976/?format=api", "name": "Bing Zhao", "email": "bingz@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210427153811.11554-13-bingz@nvidia.com/mbox/", "series": [ { "id": 16705, "url": "http://patches.dpdk.org/api/series/16705/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16705", "date": "2021-04-27T15:37:54", "name": "conntrack support in mlx5 PMD", "version": 1, "mbox": "http://patches.dpdk.org/series/16705/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/92277/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/92277/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8A023A0A0E;\n\tTue, 27 Apr 2021 17:40:05 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 995FE4129B;\n\tTue, 27 Apr 2021 17:39:14 +0200 (CEST)", "from NAM11-CO1-obe.outbound.protection.outlook.com\n (mail-co1nam11on2063.outbound.protection.outlook.com [40.107.220.63])\n by mails.dpdk.org (Postfix) with ESMTP id A10B14129B\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Bing Zhao <bingz@nvidia.com>", "To": "<viacheslavo@nvidia.com>, <matan@nvidia.com>", "CC": "<dev@dpdk.org>, <orika@nvidia.com>, <rasland@nvidia.com>", "Date": "Tue, 27 Apr 2021 18:38:06 +0300", "Message-ID": "<20210427153811.11554-13-bingz@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20210427153811.11554-1-bingz@nvidia.com>", "References": "<20210427153811.11554-1-bingz@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.145.6]", "X-ClientProxiedBy": "HQMAIL107.nvidia.com (172.20.187.13) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "b8319f42-8084-40f1-ef27-08d909929981", "X-MS-TrafficTypeDiagnostic": "BL0PR12MB4913:", "X-Microsoft-Antispam-PRVS": "\n <BL0PR12MB4913D8E22C69334BA3BAD278D0419@BL0PR12MB4913.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:6790;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n EFGrxULQmSw23rCDedEEzGONx+11dMntIxPuoqDvyjiDQsli2rmdf80cjU8mLL3VRou8QPO+Hj8Q2e58dkTJ8L1szRtqgAfHhrlkY/1iTd4kV/vgPoM+gk06HGW1wtv2l+MQah/F/HyD72Ysw4PeBy1Y4Q3iCcrH5lyMPkpqxXZLkNaJCQpL9fW7YGonqmT+lQdQJoHLN2txjy+VRMeoZkrO6uu2z6XL0FH9V8d0MhKqP7GDUiwwK6/AYwFK5gtX2zaaYuTy3AbL2ntDlgd6OGIdhKtdtvRKIoShYb6KuPfLPas+/all3pF6LvCyJQYw7WcjhA1Ka/xIXMp4EZwmYCQv2QiD0iOh1DB+2THRFnSSfHGwuUDbp1xbsU7X+N9xK8Q4L23Z6Y5G8QTFYSVU2zsFBCMzz82vXjWAtBzq3w8JIrErGB5mSej/NVtu6BWK7bRUlSU3fo6/ebYp9PpZ1JY7QNzkHAx1bC16nZHa2pw3ZQtekLAFLaoW1kkIC/Xm4FyR7yQEvNZGy0W7rE8N3t933UsaWjSQkTfuUSkQeN5Iorzbb+G1qc3TdYJDWiYOeg3+2q8E0obrfn0TIcX/6NwAW5yGq1zsHLlUEJvO0hEk0kOTnKLbZf2Cj7mjmsCFWrjFfM5DndfDYjFBNIt61w==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(39860400002)(376002)(396003)(346002)(136003)(46966006)(36840700001)(107886003)(316002)(36860700001)(1076003)(36906005)(186003)(16526019)(2616005)(4326008)(26005)(8936002)(7696005)(356005)(5660300002)(6286002)(47076005)(70206006)(7636003)(55016002)(82310400003)(82740400003)(2906002)(86362001)(110136005)(6636002)(54906003)(8676002)(336012)(70586007)(426003)(36756003)(478600001)(83380400001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "27 Apr 2021 15:39:09.3861 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n b8319f42-8084-40f1-ef27-08d909929981", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT010.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BL0PR12MB4913", "Subject": "[dpdk-dev] [PATCH 12/17] net/mlx5: add translation of CT item", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The return register of the DR action will be used for matching.\nAfter the ASO CT checking of a TCP packet, the syndrome is filled in\nthe register. Only the 8 LSB should be used. A converting from\nRTE_FLOW_CONNTRACK_FLAG* to the syndrome should be done after\nchecing the spec and mask fields.\n\nSigned-off-by: Bing Zhao <bingz@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow.h | 7 +++++\n drivers/net/mlx5/mlx5_flow_dv.c | 62 +++++++++++++++++++++++++++++++++++++++++\n 2 files changed, 69 insertions(+)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex ddfc517..c52468c 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -405,6 +405,13 @@ enum mlx5_feature_name {\n /* Maximum number of fields to modify in MODIFY_FIELD */\n #define MLX5_ACT_MAX_MOD_FIELDS 5\n \n+/* Syndrome bits definition for connection tracking. */\n+#define MLX5_CT_SYNDROME_VALID\t\t(0x0 << 6)\n+#define MLX5_CT_SYNDROME_INVALID\t(0x1 << 6)\n+#define MLX5_CT_SYNDROME_TRAP\t\t(0x2 << 6)\n+#define MLX5_CT_SYNDROME_STATE_CHANGE\t(0x1 << 1)\n+#define MLX5_CT_SYNDROME_BAD_PACKET\t(0x1 << 0)\n+\n enum mlx5_flow_drv_type {\n \tMLX5_FLOW_TYPE_MIN,\n \tMLX5_FLOW_TYPE_DV,\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 3ebeb58..eb24d5e 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -9378,6 +9378,64 @@ flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,\n \t}\n }\n \n+/*\n+ * Add connection tracking status item to matcher\n+ *\n+ * @param[in] dev\n+ * The devich to configure through.\n+ * @param[in, out] matcher\n+ * Flow matcher.\n+ * @param[in, out] key\n+ * Flow matcher value.\n+ * @param[in] item\n+ * Flow pattern to translate.\n+ */\n+static void\n+flow_dv_translate_item_aso_ct(struct rte_eth_dev *dev,\n+\t\t\t void *matcher, void *key,\n+\t\t\t const struct rte_flow_item *item)\n+{\n+\tuint32_t reg_value = 0;\n+\tint reg_id;\n+\t/* 8LSB 0b 11/0000/11, middle 4 bits are reserved. */\n+\tuint32_t reg_mask = 0;\n+\tconst struct rte_flow_item_conntrack *spec = item->spec;\n+\tconst struct rte_flow_item_conntrack *mask = item->mask;\n+\tuint32_t flags;\n+\tstruct rte_flow_error error;\n+\n+\tif (!mask)\n+\t\tmask = &rte_flow_item_conntrack_mask;\n+\tif (!spec || !mask->flags)\n+\t\treturn;\n+\tflags = spec->flags & mask->flags;\n+\t/* The conflict should be checked in the validation. */\n+\tif (flags & RTE_FLOW_CONNTRACK_PKT_STATE_VALID)\n+\t\treg_value |= MLX5_CT_SYNDROME_VALID;\n+\tif (flags & RTE_FLOW_CONNTRACK_PKT_STATE_CHANGED)\n+\t\treg_value |= MLX5_CT_SYNDROME_STATE_CHANGE;\n+\tif (flags & RTE_FLOW_CONNTRACK_PKT_STATE_INVALID)\n+\t\treg_value |= MLX5_CT_SYNDROME_INVALID;\n+\tif (flags & RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED)\n+\t\treg_value |= MLX5_CT_SYNDROME_TRAP;\n+\tif (flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD)\n+\t\treg_value |= MLX5_CT_SYNDROME_BAD_PACKET;\n+\tif (mask->flags & (RTE_FLOW_CONNTRACK_PKT_STATE_VALID |\n+\t\t\t RTE_FLOW_CONNTRACK_PKT_STATE_INVALID |\n+\t\t\t RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED))\n+\t\treg_mask |= 0xc0;\n+\tif (mask->flags & RTE_FLOW_CONNTRACK_PKT_STATE_CHANGED)\n+\t\treg_mask |= MLX5_CT_SYNDROME_STATE_CHANGE;\n+\tif (mask->flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD)\n+\t\treg_mask |= MLX5_CT_SYNDROME_BAD_PACKET;\n+\t/* The REG_C_x value could be saved during startup. */\n+\treg_id = mlx5_flow_get_reg_id(dev, MLX5_ASO_CONNTRACK, 0, &error);\n+\tif (reg_id == REG_NON)\n+\t\treturn;\n+\tflow_dv_match_meta_reg(matcher, key, (enum modify_reg)reg_id,\n+\t\t\t reg_value, reg_mask);\n+}\n+\n static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };\n \n #define HEADER_IS_ZERO(match_criteria, headers)\t\t\t\t \\\n@@ -12302,6 +12360,10 @@ flow_dv_translate(struct rte_eth_dev *dev,\n \t\t\t/* No other protocol should follow eCPRI layer. */\n \t\t\tlast_item = MLX5_FLOW_LAYER_ECPRI;\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ITEM_TYPE_CONNTRACK:\n+\t\t\tflow_dv_translate_item_aso_ct(dev, match_mask,\n+\t\t\t\t\t\t match_value, items);\n+\t\t\tbreak;\n \t\tdefault:\n \t\t\tbreak;\n \t\t}\n", "prefixes": [ "12/17" ] }