Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/92267/?format=api
{ "id": 92267, "url": "http://patches.dpdk.org/api/patches/92267/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210427153811.11554-3-bingz@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210427153811.11554-3-bingz@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210427153811.11554-3-bingz@nvidia.com", "date": "2021-04-27T15:37:56", "name": "[02/17] common/mlx5: add CT offload capability checking", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "8d95d5481626871bc4fc08f7b7dcd46833268252", "submitter": { "id": 1976, "url": "http://patches.dpdk.org/api/people/1976/?format=api", "name": "Bing Zhao", "email": "bingz@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210427153811.11554-3-bingz@nvidia.com/mbox/", "series": [ { "id": 16705, "url": "http://patches.dpdk.org/api/series/16705/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16705", "date": "2021-04-27T15:37:54", "name": "conntrack support in mlx5 PMD", "version": 1, "mbox": "http://patches.dpdk.org/series/16705/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/92267/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/92267/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2E20DA0A02;\n\tTue, 27 Apr 2021 17:38:47 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id EC4714121B;\n\tTue, 27 Apr 2021 17:38:43 +0200 (CEST)", "from NAM11-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam11on2063.outbound.protection.outlook.com [40.107.236.63])\n by mails.dpdk.org (Postfix) with ESMTP id DE4314121B\n for <dev@dpdk.org>; Tue, 27 Apr 2021 17:38:42 +0200 (CEST)", "from MWHPR14CA0030.namprd14.prod.outlook.com (2603:10b6:300:12b::16)\n by MN2PR12MB3117.namprd12.prod.outlook.com (2603:10b6:208:d1::22)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4065.25; Tue, 27 Apr\n 2021 15:38:41 +0000", "from CO1NAM11FT029.eop-nam11.prod.protection.outlook.com\n (2603:10b6:300:12b:cafe::32) by MWHPR14CA0030.outlook.office365.com\n (2603:10b6:300:12b::16) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4087.25 via Frontend\n Transport; Tue, 27 Apr 2021 15:38:41 +0000", "from mail.nvidia.com (216.228.112.34) by\n CO1NAM11FT029.mail.protection.outlook.com (10.13.174.214) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id\n 15.20.4065.21 via Frontend Transport; Tue, 27 Apr 2021 15:38:41 +0000", "from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com\n (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 27 Apr\n 2021 15:38:39 +0000" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=Qinz7JMJPe7kBXS8E5YSiZlYTOYtuHSCVfENqjPQ94RnnpTNgirEo0lUodffPM3SbYv7qZ1Vyke2UHvYUnc3ERaTQ5OUk6Mr3q5HKIXauL7Nr3g3oipAcaYurBm9NVmLorlfM25M9WDAyZDO46gPXDONqOb3gXvNXBWUn3FQSlvjgc6mmEKldxkh93CfIDvj5xsjTPhD8EApLvVkTEUKZvNLoc5dJOrB7GADZesMXsDk8a2pO3/hDpcmk82ql7tgGJd0NTW2o7ay+1jS+bdsCWqLWPQsoQNIPRm7xFb2xzCKWnM+iG5pdX3o0S124H82y59hrEGjkgGIQ2vGq8+H/g==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=/kNDqzP/rdvVAZFOK8IRZIjUZYE0ZpvDNNygeeMpZc8=;\n b=Imf3kvtwjOAZ27euaHcFBCC6b0Y3mrHGP0ZUWl1RlkYxQYZx2ysSYxwb5mlNcYohLjQ7NUnMNB5qHjmeTCy3Jdn+raGDxfk2ELQow3aiGjJ3cifdX2qlSW10ORI/6c84plDseEdWOjMsUg9+a/59Z66P3mXVEKF0ZwQVfbGjbelh/vL6ePdi5ST80rpdiNjCHxDihLYgwP4JYQQkK6XMJn7aji7P7+ryFZpGnNYt5xCO+rrCvvIzEEHknx32KSXK0oYrWBBXtLZuvgORbgbIG+8XB+1x3zk1WMEGNuvcNwU/TZwx00YdFGKit03Adx83b/OCH8QWk8uQ45Hup+acUQ==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com;\n dmarc=pass (p=none sp=none pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=/kNDqzP/rdvVAZFOK8IRZIjUZYE0ZpvDNNygeeMpZc8=;\n b=T6Qdw1m9H4SySV+W5bLalQsQC+YC9LoLQOhHmBs+UAZf01SqeBSSu7n2DGbrdAEpHTxJExQ5FUhvwNp9Tju19TwqpDUvuRIiZcbG5h9LaF859beS2yJBfgFvIw4wOlJycQgn8qSxKj+7FjFj5EOOltrL0EMwxs1VQuPMGKQNQcPyPIfMzKoYtgl+OqK8bS7uBNWGHl1H89+jblO/DH5eEhKFKJlD7lBh9qlXe01j0d1VFkdq2H3lisE5QH7dWVNAsGzqcQ8XzouQkKFdc7joL+5syuBCnAzd4wWDlLq+uEISm/0VNwFAA5x3rsTKX4GF0p/k5DdpvsNERTe3kYdoNg==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.112.34)\n smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed)\n header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "Bing Zhao <bingz@nvidia.com>", "To": "<viacheslavo@nvidia.com>, <matan@nvidia.com>", "CC": "<dev@dpdk.org>, <orika@nvidia.com>, <rasland@nvidia.com>", "Date": "Tue, 27 Apr 2021 18:37:56 +0300", "Message-ID": "<20210427153811.11554-3-bingz@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20210427153811.11554-1-bingz@nvidia.com>", "References": "<20210427153811.11554-1-bingz@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.145.6]", "X-ClientProxiedBy": "HQMAIL107.nvidia.com (172.20.187.13) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "bc5d230f-4b8a-467b-f2d0-08d9099288b5", "X-MS-TrafficTypeDiagnostic": "MN2PR12MB3117:", "X-Microsoft-Antispam-PRVS": "\n <MN2PR12MB3117B611502068D3E1B71963D0419@MN2PR12MB3117.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:6108;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n hHZWVPN44lGA0hx78zsFGDUneI+nHEat7G1L28nV4QpNw3EXpI3uRe7jUjx0FFHB7aB7n9bGGY0DPokws0ZwxlMEcCk2JYXn+ObTS2WQL/SXFYzAelbO4D5IBQ5WMidD9D1WtrgLl/nc/oIh4NSy9hpI3YH/B3nMszd5+tZZ2ByQlVzTiF+c7l5cbYSh7KE6ocber9K+7ZVZT77nsiUgYm6nQE/uD4ibpNdBO4PuiA03pYxeM84fQ+oBaCK5+xv5aasT+Lik+/8jz9LZ/ndcJw1lfOzb5a7YiZALE1Heft5WO4I7J0FKgGtZQ+q4Q9kGYOYh7/+1gEdwsPqfItbxKl5BAxmEgYiO2VmEZK0y5o+KcRELd6R89YgVHbjapt3OOzLJa0oEuh5DM+d02j3S6be5NJ8jqa+Ba2XF8oOLwRNEGrvU5i58ZRBIoQ2Pj/gD6Ca1YfN+RZCPrQH47eHkKx2MrJiA5BYUXNl1CH9paFgWXQNpSmPX5enT4XCf23YS+Iz5r5y+sTKaipClF861+8jWUta7l70psdC/pRGZR+7lrKOOydd/5bnnjjxf2gSqy8hu45Jh71S3L62SOcC0nicT6uaQKh6tap0SjjztjviYaOZILa/wU7bj9Z4Oh49eTEOoXXgYa8evZs6TAbjQ0pPxKWYCLmZsBaZJL2o+jAA=", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(346002)(376002)(396003)(136003)(39860400002)(46966006)(36840700001)(8676002)(16526019)(5660300002)(6286002)(426003)(1076003)(107886003)(86362001)(70206006)(478600001)(82740400003)(70586007)(336012)(6666004)(26005)(2906002)(36860700001)(47076005)(4326008)(7696005)(54906003)(83380400001)(8936002)(7636003)(36906005)(110136005)(55016002)(36756003)(2616005)(316002)(82310400003)(186003)(6636002)(356005);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "27 Apr 2021 15:38:41.2017 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n bc5d230f-4b8a-467b-f2d0-08d9099288b5", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT029.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN2PR12MB3117", "Subject": "[dpdk-dev] [PATCH 02/17] common/mlx5: add CT offload capability\n checking", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "During startup, the ASO connection tracking offload capability could\nbe queried via HCA_CAP_QUERY command. If the HW doesn't support ASO\nCT, the value would be 0 by default. The following initialization\nshould be skipped and the creation of the CT object should return\na failure directly.\n\nThe following CT creation should also check this capability. With\nthe old driver, the pre-processing macro should be used in order to\nmake the compiling pass.\n\nSigned-off-by: Bing Zhao <bingz@nvidia.com>\n---\n drivers/common/mlx5/linux/meson.build | 2 ++\n drivers/common/mlx5/mlx5_devx_cmds.c | 3 +++\n drivers/common/mlx5/mlx5_devx_cmds.h | 1 +\n drivers/common/mlx5/mlx5_prm.h | 3 +++\n 4 files changed, 9 insertions(+)", "diff": "diff --git a/drivers/common/mlx5/linux/meson.build b/drivers/common/mlx5/linux/meson.build\nindex 3334bd5..007834a 100644\n--- a/drivers/common/mlx5/linux/meson.build\n+++ b/drivers/common/mlx5/linux/meson.build\n@@ -189,6 +189,8 @@ has_sym_args = [\n 'MLX5_WQE_UMR_CTRL_FLAG_INLINE' ],\n [ 'HAVE_MLX5_DR_FLOW_DUMP_RULE', 'infiniband/mlx5dv.h',\n 'mlx5dv_dump_dr_rule' ],\n+ [ 'HAVE_MLX5_DR_ACTION_ASO_CT', 'infiniband/mlx5dv.h',\n+ 'MLX5DV_DR_ACTION_FLAGS_ASO_CT_DIRECTION_INITIATOR' ],\n ]\n config = configuration_data()\n foreach arg:has_sym_args\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 6c6f439..4300536 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -760,6 +760,9 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \t\tMLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled);\n \tattr->umr_modify_entity_size_disabled =\n \t\tMLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled);\n+\tattr->ct_offload = !!(MLX5_GET64(cmd_hca_cap, hcattr,\n+\t\t\t\t\t general_obj_types) &\n+\t\t\t MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD);\n \tif (attr->qos.sup) {\n \t\tMLX5_SET(query_hca_cap_in, in, op_mod,\n \t\t\t MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex eee8fee..956b0b1 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -136,6 +136,7 @@ struct mlx5_hca_attr {\n \tuint32_t qp_ts_format:2;\n \tuint32_t regex:1;\n \tuint32_t reg_c_preserve:1;\n+\tuint32_t ct_offload:1; /* General obj type ASO CT offload supported. */\n \tuint32_t regexp_num_of_engines;\n \tuint32_t log_max_ft_sampler_num:8;\n \tuint32_t geneve_tlv_opt;\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 853eb58..d9987e1 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -1134,6 +1134,8 @@ enum {\n \t\t\t(1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO)\n #define MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT \\\n \t\t\t(1ULL << MLX5_OBJ_TYPE_GENEVE_TLV_OPT)\n+#define MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD \\\n+\t\t\t(1ULL << MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD)\n \n enum {\n \tMLX5_HCA_CAP_OPMOD_GET_MAX = 0,\n@@ -2449,6 +2451,7 @@ enum {\n \tMLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022,\n \tMLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO = 0x0024,\n \tMLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO = 0x0025,\n+\tMLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD = 0x0031,\n };\n \n struct mlx5_ifc_general_obj_in_cmd_hdr_bits {\n", "prefixes": [ "02/17" ] }