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GET /api/patches/92219/?format=api
{ "id": 92219, "url": "http://patches.dpdk.org/api/patches/92219/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210426174441.2302-34-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210426174441.2302-34-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210426174441.2302-34-pbhagavatula@marvell.com", "date": "2021-04-26T17:44:40", "name": "[v2,33/33] event/cnxk: add devargs to control timer adapters", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ba678059565f6869bda79f996ba91ed996f810b0", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210426174441.2302-34-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 16682, "url": "http://patches.dpdk.org/api/series/16682/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16682", "date": "2021-04-26T17:44:07", "name": "Marvell CNXK Event device Driver", "version": 2, "mbox": "http://patches.dpdk.org/series/16682/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/92219/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/92219/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 83ED5A0548;\n\tMon, 26 Apr 2021 19:49:00 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 4E18041296;\n\tMon, 26 Apr 2021 19:46:55 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 54D3A4127B\n for <dev@dpdk.org>; Mon, 26 Apr 2021 19:46:51 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 13QHiwMB030142 for <dev@dpdk.org>; Mon, 26 Apr 2021 10:46:50 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 385tvvhdn2-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Mon, 26 Apr 2021 10:46:50 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Mon, 26 Apr 2021 10:46:48 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Mon, 26 Apr 2021 10:46:48 -0700", "from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176])\n by maili.marvell.com (Postfix) with ESMTP id E26725B6C96;\n Mon, 26 Apr 2021 10:46:46 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=kXjWU/UILXez5JGxFTBZWL6fMlH0civySxsQUTt0nf8=;\n b=LhHFZ6dRY79hrHz1gPH2SdwaitEZr2Za6dNjN2l/KFI6EL9HHB4nHHMXiLVdWbgopcfb\n SJpUtKF9DWpIbJRgf++zmIk07kDrx8aLcyY8/2tZNM7iiBaetzDcD+hGX7JQ++kww18A\n 1OUwl1LE2ggFZnjpSj+Zo1WzKPCIa0D5DuxBuzIthf6pf5WQq7mkBXaH4tg3ANK7fGRx\n 7aqkWAAXNWJF6K6H5MgvMPSoKvFgb/kuYOxni1F7dhPdP9eJGubYCDixYuqoVSlBKtZ2\n ZoFdyEyz8bXkKRkWECYirGFQi9rzyLd+BGK41Nox/HTyG8DwHZKGxmO7bL4BTRukoI20 Ww==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>, \"Shijith\n Thotton\" <sthotton@marvell.com>", "CC": "<dev@dpdk.org>", "Date": "Mon, 26 Apr 2021 23:14:40 +0530", "Message-ID": "<20210426174441.2302-34-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210426174441.2302-1-pbhagavatula@marvell.com>", "References": "<20210306162942.6845-1-pbhagavatula@marvell.com>\n <20210426174441.2302-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "_B-VvlZAPigGZBYggi2_vtcjUITn7JIT", "X-Proofpoint-ORIG-GUID": "_B-VvlZAPigGZBYggi2_vtcjUITn7JIT", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761\n definitions=2021-04-26_09:2021-04-26,\n 2021-04-26 signatures=0", "Subject": "[dpdk-dev] [PATCH v2 33/33] event/cnxk: add devargs to control\n timer adapters", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Shijith Thotton <sthotton@marvell.com>\n\nAdd devargs to control each event timer adapter i.e. TIM rings internal\nparameters uniquely. The following dict format is expected\n[ring-chnk_slots-disable_npa-stats_ena]. 0 represents default values.\n\nExample:\n\t--dev \"0002:1e:00.0,tim_ring_ctl=[2-1023-1-0]\"\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\nSigned-off-by: Shijith Thotton <sthotton@marvell.com>\n---\n doc/guides/eventdevs/cnxk.rst | 11 ++++\n drivers/event/cnxk/cnxk_tim_evdev.c | 96 ++++++++++++++++++++++++++++-\n drivers/event/cnxk/cnxk_tim_evdev.h | 10 +++\n 3 files changed, 116 insertions(+), 1 deletion(-)", "diff": "diff --git a/doc/guides/eventdevs/cnxk.rst b/doc/guides/eventdevs/cnxk.rst\nindex cfa743da1..c42784a3b 100644\n--- a/doc/guides/eventdevs/cnxk.rst\n+++ b/doc/guides/eventdevs/cnxk.rst\n@@ -135,6 +135,17 @@ Runtime Config Options\n \n -a 0002:0e:00.0,tim_rings_lmt=5\n \n+- ``TIM ring control internal parameters``\n+\n+ When using multiple TIM rings the ``tim_ring_ctl`` devargs can be used to\n+ control each TIM rings internal parameters uniquely. The following dict\n+ format is expected [ring-chnk_slots-disable_npa-stats_ena]. 0 represents\n+ default values.\n+\n+ For Example::\n+\n+ -a 0002:0e:00.0,tim_ring_ctl=[2-1023-1-0]\n+\n Debugging Options\n -----------------\n \ndiff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c\nindex 7b28969c9..fdc78270d 100644\n--- a/drivers/event/cnxk/cnxk_tim_evdev.c\n+++ b/drivers/event/cnxk/cnxk_tim_evdev.c\n@@ -121,7 +121,7 @@ cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr)\n \tstruct rte_event_timer_adapter_conf *rcfg = &adptr->data->conf;\n \tstruct cnxk_tim_evdev *dev = cnxk_tim_priv_get();\n \tstruct cnxk_tim_ring *tim_ring;\n-\tint rc;\n+\tint i, rc;\n \n \tif (dev == NULL)\n \t\treturn -ENODEV;\n@@ -165,6 +165,20 @@ cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr)\n \ttim_ring->disable_npa = dev->disable_npa;\n \ttim_ring->enable_stats = dev->enable_stats;\n \n+\tfor (i = 0; i < dev->ring_ctl_cnt; i++) {\n+\t\tstruct cnxk_tim_ctl *ring_ctl = &dev->ring_ctl_data[i];\n+\n+\t\tif (ring_ctl->ring == tim_ring->ring_id) {\n+\t\t\ttim_ring->chunk_sz =\n+\t\t\t\tring_ctl->chunk_slots ?\n+\t\t\t\t\t((uint32_t)(ring_ctl->chunk_slots + 1) *\n+\t\t\t\t\t CNXK_TIM_CHUNK_ALIGNMENT) :\n+\t\t\t\t\t tim_ring->chunk_sz;\n+\t\t\ttim_ring->enable_stats = ring_ctl->enable_stats;\n+\t\t\ttim_ring->disable_npa = ring_ctl->disable_npa;\n+\t\t}\n+\t}\n+\n \tif (tim_ring->disable_npa) {\n \t\ttim_ring->nb_chunks =\n \t\t\ttim_ring->nb_timers /\n@@ -368,6 +382,84 @@ cnxk_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags,\n \treturn 0;\n }\n \n+static void\n+cnxk_tim_parse_ring_param(char *value, void *opaque)\n+{\n+\tstruct cnxk_tim_evdev *dev = opaque;\n+\tstruct cnxk_tim_ctl ring_ctl = {0};\n+\tchar *tok = strtok(value, \"-\");\n+\tstruct cnxk_tim_ctl *old_ptr;\n+\tuint16_t *val;\n+\n+\tval = (uint16_t *)&ring_ctl;\n+\n+\tif (!strlen(value))\n+\t\treturn;\n+\n+\twhile (tok != NULL) {\n+\t\t*val = atoi(tok);\n+\t\ttok = strtok(NULL, \"-\");\n+\t\tval++;\n+\t}\n+\n+\tif (val != (&ring_ctl.enable_stats + 1)) {\n+\t\tplt_err(\"Invalid ring param expected [ring-chunk_sz-disable_npa-enable_stats]\");\n+\t\treturn;\n+\t}\n+\n+\tdev->ring_ctl_cnt++;\n+\told_ptr = dev->ring_ctl_data;\n+\tdev->ring_ctl_data =\n+\t\trte_realloc(dev->ring_ctl_data,\n+\t\t\t sizeof(struct cnxk_tim_ctl) * dev->ring_ctl_cnt, 0);\n+\tif (dev->ring_ctl_data == NULL) {\n+\t\tdev->ring_ctl_data = old_ptr;\n+\t\tdev->ring_ctl_cnt--;\n+\t\treturn;\n+\t}\n+\n+\tdev->ring_ctl_data[dev->ring_ctl_cnt - 1] = ring_ctl;\n+}\n+\n+static void\n+cnxk_tim_parse_ring_ctl_list(const char *value, void *opaque)\n+{\n+\tchar *s = strdup(value);\n+\tchar *start = NULL;\n+\tchar *end = NULL;\n+\tchar *f = s;\n+\n+\twhile (*s) {\n+\t\tif (*s == '[')\n+\t\t\tstart = s;\n+\t\telse if (*s == ']')\n+\t\t\tend = s;\n+\n+\t\tif (start && start < end) {\n+\t\t\t*end = 0;\n+\t\t\tcnxk_tim_parse_ring_param(start + 1, opaque);\n+\t\t\tstart = end;\n+\t\t\ts = end;\n+\t\t}\n+\t\ts++;\n+\t}\n+\n+\tfree(f);\n+}\n+\n+static int\n+cnxk_tim_parse_kvargs_dict(const char *key, const char *value, void *opaque)\n+{\n+\tRTE_SET_USED(key);\n+\n+\t/* Dict format [ring-chunk_sz-disable_npa-enable_stats] use '-' as ','\n+\t * isn't allowed. 0 represents default.\n+\t */\n+\tcnxk_tim_parse_ring_ctl_list(value, opaque);\n+\n+\treturn 0;\n+}\n+\n static void\n cnxk_tim_parse_devargs(struct rte_devargs *devargs, struct cnxk_tim_evdev *dev)\n {\n@@ -388,6 +480,8 @@ cnxk_tim_parse_devargs(struct rte_devargs *devargs, struct cnxk_tim_evdev *dev)\n \t\t\t &dev->enable_stats);\n \trte_kvargs_process(kvlist, CNXK_TIM_RINGS_LMT, &parse_kvargs_value,\n \t\t\t &dev->min_ring_cnt);\n+\trte_kvargs_process(kvlist, CNXK_TIM_RING_CTL,\n+\t\t\t &cnxk_tim_parse_kvargs_dict, &dev);\n \n \trte_kvargs_free(kvlist);\n }\ndiff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h\nindex 7aa9650c1..d0df226ed 100644\n--- a/drivers/event/cnxk/cnxk_tim_evdev.h\n+++ b/drivers/event/cnxk/cnxk_tim_evdev.h\n@@ -38,6 +38,7 @@\n #define CNXK_TIM_CHNK_SLOTS \"tim_chnk_slots\"\n #define CNXK_TIM_STATS_ENA \"tim_stats_ena\"\n #define CNXK_TIM_RINGS_LMT \"tim_rings_lmt\"\n+#define CNXK_TIM_RING_CTL \"tim_ring_ctl\"\n \n #define CNXK_TIM_SP\t 0x1\n #define CNXK_TIM_MP\t 0x2\n@@ -75,6 +76,13 @@\n #define TIM_BUCKET_SEMA_WLOCK \\\n \t(TIM_BUCKET_CHUNK_REMAIN | (1ull << TIM_BUCKET_W1_S_LOCK))\n \n+struct cnxk_tim_ctl {\n+\tuint16_t ring;\n+\tuint16_t chunk_slots;\n+\tuint16_t disable_npa;\n+\tuint16_t enable_stats;\n+};\n+\n struct cnxk_tim_evdev {\n \tstruct roc_tim tim;\n \tstruct rte_eventdev *event_dev;\n@@ -85,6 +93,8 @@ struct cnxk_tim_evdev {\n \tuint16_t chunk_slots;\n \tuint16_t min_ring_cnt;\n \tuint8_t enable_stats;\n+\tuint16_t ring_ctl_cnt;\n+\tstruct cnxk_tim_ctl *ring_ctl_data;\n };\n \n enum cnxk_tim_clk_src {\n", "prefixes": [ "v2", "33/33" ] }