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{
    "id": 92195,
    "url": "http://patches.dpdk.org/api/patches/92195/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210426174441.2302-10-pbhagavatula@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20210426174441.2302-10-pbhagavatula@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20210426174441.2302-10-pbhagavatula@marvell.com",
    "date": "2021-04-26T17:44:16",
    "name": "[v2,09/33] event/cnxk: add devargs to control SSO HWGRP QoS",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "35b31b5fb2c762088c4007bfdbef69b5b72410de",
    "submitter": {
        "id": 1183,
        "url": "http://patches.dpdk.org/api/people/1183/?format=api",
        "name": "Pavan Nikhilesh Bhagavatula",
        "email": "pbhagavatula@marvell.com"
    },
    "delegate": {
        "id": 310,
        "url": "http://patches.dpdk.org/api/users/310/?format=api",
        "username": "jerin",
        "first_name": "Jerin",
        "last_name": "Jacob",
        "email": "jerinj@marvell.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210426174441.2302-10-pbhagavatula@marvell.com/mbox/",
    "series": [
        {
            "id": 16682,
            "url": "http://patches.dpdk.org/api/series/16682/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16682",
            "date": "2021-04-26T17:44:07",
            "name": "Marvell CNXK Event device Driver",
            "version": 2,
            "mbox": "http://patches.dpdk.org/series/16682/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/92195/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/92195/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
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        "From": "<pbhagavatula@marvell.com>",
        "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>, \"Shijith\n Thotton\" <sthotton@marvell.com>",
        "CC": "<dev@dpdk.org>",
        "Date": "Mon, 26 Apr 2021 23:14:16 +0530",
        "Message-ID": "<20210426174441.2302-10-pbhagavatula@marvell.com>",
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        "References": "<20210306162942.6845-1-pbhagavatula@marvell.com>\n <20210426174441.2302-1-pbhagavatula@marvell.com>",
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        "Subject": "[dpdk-dev] [PATCH v2 09/33] event/cnxk: add devargs to control SSO\n HWGRP QoS",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
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        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Shijith Thotton <sthotton@marvell.com>\n\nSSO HWGRPs i.e. queue uses DRAM & SRAM buffers to hold in-flight\nevents. By default the buffers are assigned to the SSO HWGRPs to\nsatisfy minimum HW requirements. SSO is free to assign the remaining\nbuffers to HWGRPs based on a preconfigured threshold.\nWe can control the QoS of SSO HWGRP by modifying the above mentioned\nthresholds. HWGRPs that have higher importance can be assigned higher\nthresholds than the rest.\n\nExample:\n        --dev \"0002:0e:00.0,qos=[1-50-50-50]\" // [Qx-XAQ-TAQ-IAQ]\n\nQx  -> Event queue Aka SSO GGRP.\nXAQ -> DRAM In-flights.\nTAQ & IAQ -> SRAM In-flights.\n\nThe values need to be expressed in terms of percentages, 0 represents\ndefault.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\nSigned-off-by: Shijith Thotton <sthotton@marvell.com>\n---\n doc/guides/eventdevs/cnxk.rst       | 16 ++++++\n drivers/event/cnxk/cn10k_eventdev.c |  3 +-\n drivers/event/cnxk/cn9k_eventdev.c  |  3 +-\n drivers/event/cnxk/cnxk_eventdev.c  | 78 +++++++++++++++++++++++++++++\n drivers/event/cnxk/cnxk_eventdev.h  | 12 ++++-\n 5 files changed, 109 insertions(+), 3 deletions(-)",
    "diff": "diff --git a/doc/guides/eventdevs/cnxk.rst b/doc/guides/eventdevs/cnxk.rst\nindex 569fce4cb..cf2156333 100644\n--- a/doc/guides/eventdevs/cnxk.rst\n+++ b/doc/guides/eventdevs/cnxk.rst\n@@ -55,6 +55,22 @@ Runtime Config Options\n \n     -a 0002:0e:00.0,xae_cnt=16384\n \n+- ``Event Group QoS support``\n+\n+  SSO GGRPs i.e. queue uses DRAM & SRAM buffers to hold in-flight\n+  events. By default the buffers are assigned to the SSO GGRPs to\n+  satisfy minimum HW requirements. SSO is free to assign the remaining\n+  buffers to GGRPs based on a preconfigured threshold.\n+  We can control the QoS of SSO GGRP by modifying the above mentioned\n+  thresholds. GGRPs that have higher importance can be assigned higher\n+  thresholds than the rest. The dictionary format is as follows\n+  [Qx-XAQ-TAQ-IAQ][Qz-XAQ-TAQ-IAQ] expressed in percentages, 0 represents\n+  default.\n+\n+  For example::\n+\n+    -a 0002:0e:00.0,qos=[1-50-50-50]\n+\n Debugging Options\n -----------------\n \ndiff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c\nindex 1b278360f..47eb8898b 100644\n--- a/drivers/event/cnxk/cn10k_eventdev.c\n+++ b/drivers/event/cnxk/cn10k_eventdev.c\n@@ -143,4 +143,5 @@ static struct rte_pci_driver cn10k_pci_sso = {\n RTE_PMD_REGISTER_PCI(event_cn10k, cn10k_pci_sso);\n RTE_PMD_REGISTER_PCI_TABLE(event_cn10k, cn10k_pci_sso_map);\n RTE_PMD_REGISTER_KMOD_DEP(event_cn10k, \"vfio-pci\");\n-RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT \"=<int>\");\n+RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT \"=<int>\"\n+\t\t\t      CNXK_SSO_GGRP_QOS \"=<string>\");\ndiff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c\nindex 8dfcf35b4..43c045d43 100644\n--- a/drivers/event/cnxk/cn9k_eventdev.c\n+++ b/drivers/event/cnxk/cn9k_eventdev.c\n@@ -146,4 +146,5 @@ static struct rte_pci_driver cn9k_pci_sso = {\n RTE_PMD_REGISTER_PCI(event_cn9k, cn9k_pci_sso);\n RTE_PMD_REGISTER_PCI_TABLE(event_cn9k, cn9k_pci_sso_map);\n RTE_PMD_REGISTER_KMOD_DEP(event_cn9k, \"vfio-pci\");\n-RTE_PMD_REGISTER_PARAM_STRING(event_cn9k, CNXK_SSO_XAE_CNT \"=<int>\");\n+RTE_PMD_REGISTER_PARAM_STRING(event_cn9k, CNXK_SSO_XAE_CNT \"=<int>\"\n+\t\t\t      CNXK_SSO_GGRP_QOS \"=<string>\");\ndiff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c\nindex 28a03aeab..4cb5359a8 100644\n--- a/drivers/event/cnxk/cnxk_eventdev.c\n+++ b/drivers/event/cnxk/cnxk_eventdev.c\n@@ -225,6 +225,82 @@ cnxk_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id,\n \tport_conf->enqueue_depth = 1;\n }\n \n+static void\n+parse_queue_param(char *value, void *opaque)\n+{\n+\tstruct cnxk_sso_qos queue_qos = {0};\n+\tuint8_t *val = (uint8_t *)&queue_qos;\n+\tstruct cnxk_sso_evdev *dev = opaque;\n+\tchar *tok = strtok(value, \"-\");\n+\tstruct cnxk_sso_qos *old_ptr;\n+\n+\tif (!strlen(value))\n+\t\treturn;\n+\n+\twhile (tok != NULL) {\n+\t\t*val = atoi(tok);\n+\t\ttok = strtok(NULL, \"-\");\n+\t\tval++;\n+\t}\n+\n+\tif (val != (&queue_qos.iaq_prcnt + 1)) {\n+\t\tplt_err(\"Invalid QoS parameter expected [Qx-XAQ-TAQ-IAQ]\");\n+\t\treturn;\n+\t}\n+\n+\tdev->qos_queue_cnt++;\n+\told_ptr = dev->qos_parse_data;\n+\tdev->qos_parse_data = rte_realloc(\n+\t\tdev->qos_parse_data,\n+\t\tsizeof(struct cnxk_sso_qos) * dev->qos_queue_cnt, 0);\n+\tif (dev->qos_parse_data == NULL) {\n+\t\tdev->qos_parse_data = old_ptr;\n+\t\tdev->qos_queue_cnt--;\n+\t\treturn;\n+\t}\n+\tdev->qos_parse_data[dev->qos_queue_cnt - 1] = queue_qos;\n+}\n+\n+static void\n+parse_qos_list(const char *value, void *opaque)\n+{\n+\tchar *s = strdup(value);\n+\tchar *start = NULL;\n+\tchar *end = NULL;\n+\tchar *f = s;\n+\n+\twhile (*s) {\n+\t\tif (*s == '[')\n+\t\t\tstart = s;\n+\t\telse if (*s == ']')\n+\t\t\tend = s;\n+\n+\t\tif (start && start < end) {\n+\t\t\t*end = 0;\n+\t\t\tparse_queue_param(start + 1, opaque);\n+\t\t\ts = end;\n+\t\t\tstart = end;\n+\t\t}\n+\t\ts++;\n+\t}\n+\n+\tfree(f);\n+}\n+\n+static int\n+parse_sso_kvargs_dict(const char *key, const char *value, void *opaque)\n+{\n+\tRTE_SET_USED(key);\n+\n+\t/* Dict format [Qx-XAQ-TAQ-IAQ][Qz-XAQ-TAQ-IAQ] use '-' cause ','\n+\t * isn't allowed. Everything is expressed in percentages, 0 represents\n+\t * default.\n+\t */\n+\tparse_qos_list(value, opaque);\n+\n+\treturn 0;\n+}\n+\n static void\n cnxk_sso_parse_devargs(struct cnxk_sso_evdev *dev, struct rte_devargs *devargs)\n {\n@@ -238,6 +314,8 @@ cnxk_sso_parse_devargs(struct cnxk_sso_evdev *dev, struct rte_devargs *devargs)\n \n \trte_kvargs_process(kvlist, CNXK_SSO_XAE_CNT, &parse_kvargs_value,\n \t\t\t   &dev->xae_cnt);\n+\trte_kvargs_process(kvlist, CNXK_SSO_GGRP_QOS, &parse_sso_kvargs_dict,\n+\t\t\t   dev);\n \trte_kvargs_free(kvlist);\n }\n \ndiff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h\nindex 72b0ff3f8..4a2fa73fe 100644\n--- a/drivers/event/cnxk/cnxk_eventdev.h\n+++ b/drivers/event/cnxk/cnxk_eventdev.h\n@@ -14,7 +14,8 @@\n \n #include \"roc_api.h\"\n \n-#define CNXK_SSO_XAE_CNT \"xae_cnt\"\n+#define CNXK_SSO_XAE_CNT  \"xae_cnt\"\n+#define CNXK_SSO_GGRP_QOS \"qos\"\n \n #define USEC2NSEC(__us) ((__us)*1E3)\n \n@@ -23,6 +24,13 @@\n #define CNXK_SSO_XAQ_CACHE_CNT (0x7)\n #define CNXK_SSO_XAQ_SLACK     (8)\n \n+struct cnxk_sso_qos {\n+\tuint16_t queue;\n+\tuint8_t xaq_prcnt;\n+\tuint8_t taq_prcnt;\n+\tuint8_t iaq_prcnt;\n+};\n+\n struct cnxk_sso_evdev {\n \tstruct roc_sso sso;\n \tuint8_t max_event_queues;\n@@ -41,6 +49,8 @@ struct cnxk_sso_evdev {\n \tstruct rte_mempool *xaq_pool;\n \t/* Dev args */\n \tuint32_t xae_cnt;\n+\tuint8_t qos_queue_cnt;\n+\tstruct cnxk_sso_qos *qos_parse_data;\n \t/* CN9K */\n \tuint8_t dual_ws;\n } __rte_cache_aligned;\n",
    "prefixes": [
        "v2",
        "09/33"
    ]
}