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GET /api/patches/92187/?format=api
{ "id": 92187, "url": "http://patches.dpdk.org/api/patches/92187/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210426174441.2302-2-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210426174441.2302-2-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210426174441.2302-2-pbhagavatula@marvell.com", "date": "2021-04-26T17:44:08", "name": "[v2,01/33] event/cnxk: add build infra and device setup", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "79aaa8f92d06aac7077f9ba8c8212bdf51e50dc1", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210426174441.2302-2-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 16682, "url": "http://patches.dpdk.org/api/series/16682/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16682", "date": "2021-04-26T17:44:07", "name": "Marvell CNXK Event device Driver", "version": 2, "mbox": "http://patches.dpdk.org/series/16682/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/92187/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/92187/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 67E91A0548;\n\tMon, 26 Apr 2021 19:45:03 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 9922B411F2;\n\tMon, 26 Apr 2021 19:45:01 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 6747D411F0\n for <dev@dpdk.org>; Mon, 26 Apr 2021 19:45:00 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 13QHivaM030137; Mon, 26 Apr 2021 10:44:57 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 385tvvhdce-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Mon, 26 Apr 2021 10:44:57 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Mon, 26 Apr 2021 10:44:55 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Mon, 26 Apr 2021 10:44:54 -0700", "from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176])\n by maili.marvell.com (Postfix) with ESMTP id B6C1C5B6C96;\n Mon, 26 Apr 2021 10:44:51 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=zko0boMJTtk65jXkYcpN3sAHxZUF0j0P/qel5P4wYgY=;\n b=E1PE36OvEMoA91LdpH53FSj21hrsVzwVHf1F8XT5SEbIRxomVIHHiLtFUgf0162h4UUo\n 7lTAvQiElUwi7IS/Ftrsh73E6kRp9CZyWoVbLm4rcrW1zEiu5ASpR0P43oZWSPyFURK+\n lFXjyEodia2bQuTbDGdWUOPxUzNPO+koGh/cj67xvl0yyuT5WOirBKfPc0T18UhhVoS/\n ozB40l3NLCJjc67xBsKbhF0bmDBkkqtlXx/dgi2qejrzM1J+nWpLqxej+of02M9aJDSp\n uevnnmdzRAdQq6tYEuFJo2728AUQYwEexZOtuFnu7FIq2deP0pZxf0qGRUKqCVMkkJGY GA==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Thomas Monjalon <thomas@monjalon.net>, \"Pavan\n Nikhilesh\" <pbhagavatula@marvell.com>, Shijith Thotton\n <sthotton@marvell.com>, Ray Kinsella <mdr@ashroe.eu>, Neil Horman\n <nhorman@tuxdriver.com>, \"Anatoly Burakov\" <anatoly.burakov@intel.com>", "CC": "<dev@dpdk.org>", "Date": "Mon, 26 Apr 2021 23:14:08 +0530", "Message-ID": "<20210426174441.2302-2-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210426174441.2302-1-pbhagavatula@marvell.com>", "References": "<20210306162942.6845-1-pbhagavatula@marvell.com>\n <20210426174441.2302-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "rsl9gsFPSU4CLveO_0f9EJiyTWpMnN9b", "X-Proofpoint-ORIG-GUID": "rsl9gsFPSU4CLveO_0f9EJiyTWpMnN9b", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761\n definitions=2021-04-26_09:2021-04-26,\n 2021-04-26 signatures=0", "Subject": "[dpdk-dev] [PATCH v2 01/33] event/cnxk: add build infra and device\n setup", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd meson build infra structure along with the event device\nSSO initialization and teardown functions.\n\nSigned-off-by: Shijith Thotton <sthotton@marvell.com>\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n MAINTAINERS | 6 +++\n doc/guides/eventdevs/cnxk.rst | 55 ++++++++++++++++++++++++\n doc/guides/eventdevs/index.rst | 1 +\n drivers/event/cnxk/cnxk_eventdev.c | 68 ++++++++++++++++++++++++++++++\n drivers/event/cnxk/cnxk_eventdev.h | 39 +++++++++++++++++\n drivers/event/cnxk/meson.build | 13 ++++++\n drivers/event/cnxk/version.map | 3 ++\n drivers/event/meson.build | 1 +\n 8 files changed, 186 insertions(+)\n create mode 100644 doc/guides/eventdevs/cnxk.rst\n create mode 100644 drivers/event/cnxk/cnxk_eventdev.c\n create mode 100644 drivers/event/cnxk/cnxk_eventdev.h\n create mode 100644 drivers/event/cnxk/meson.build\n create mode 100644 drivers/event/cnxk/version.map", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex 44f3d322e..d1ae33d48 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -1224,6 +1224,12 @@ M: Jerin Jacob <jerinj@marvell.com>\n F: drivers/event/octeontx2/\n F: doc/guides/eventdevs/octeontx2.rst\n \n+Marvell OCTEON CNXK\n+M: Pavan Nikhilesh <pbhagavatula@marvell.com>\n+M: Shijith Thotton <sthotton@marvell.com>\n+F: drivers/event/cnxk/\n+F: doc/guides/eventdevs/cnxk.rst\n+\n NXP DPAA eventdev\n M: Hemant Agrawal <hemant.agrawal@nxp.com>\n M: Nipun Gupta <nipun.gupta@nxp.com>\ndiff --git a/doc/guides/eventdevs/cnxk.rst b/doc/guides/eventdevs/cnxk.rst\nnew file mode 100644\nindex 000000000..e94225bd3\n--- /dev/null\n+++ b/doc/guides/eventdevs/cnxk.rst\n@@ -0,0 +1,55 @@\n+.. SPDX-License-Identifier: BSD-3-Clause\n+ Copyright(c) 2021 Marvell International Ltd.\n+\n+OCTEON CNXK SSO Eventdev Driver\n+==========================\n+\n+The SSO PMD (**librte_event_cnxk**) and provides poll mode\n+eventdev driver support for the inbuilt event device found in the\n+**Marvell OCTEON CNXK** SoC family.\n+\n+More information about OCTEON CNXK SoC can be found at `Marvell Official Website\n+<https://www.marvell.com/embedded-processors/infrastructure-processors/>`_.\n+\n+Supported OCTEON CNXK SoCs\n+--------------------------\n+\n+- CN9XX\n+- CN10XX\n+\n+Features\n+--------\n+\n+Features of the OCTEON CNXK SSO PMD are:\n+\n+- 256 Event queues\n+- 26 (dual) and 52 (single) Event ports on CN10XX\n+- 52 Event ports on CN9XX\n+- HW event scheduler\n+- Supports 1M flows per event queue\n+- Flow based event pipelining\n+- Flow pinning support in flow based event pipelining\n+- Queue based event pipelining\n+- Supports ATOMIC, ORDERED, PARALLEL schedule types per flow\n+- Event scheduling QoS based on event queue priority\n+- Open system with configurable amount of outstanding events limited only by\n+ DRAM\n+- HW accelerated dequeue timeout support to enable power management\n+\n+Prerequisites and Compilation procedure\n+---------------------------------------\n+\n+ See :doc:`../platform/cnxk` for setup information.\n+\n+Debugging Options\n+-----------------\n+\n+.. _table_octeon_cnxk_event_debug_options:\n+\n+.. table:: OCTEON CNXK event device debug options\n+\n+ +---+------------+-------------------------------------------------------+\n+ | # | Component | EAL log command |\n+ +===+============+=======================================================+\n+ | 1 | SSO | --log-level='pmd\\.event\\.cnxk,8' |\n+ +---+------------+-------------------------------------------------------+\ndiff --git a/doc/guides/eventdevs/index.rst b/doc/guides/eventdevs/index.rst\nindex 738788d9e..214302539 100644\n--- a/doc/guides/eventdevs/index.rst\n+++ b/doc/guides/eventdevs/index.rst\n@@ -11,6 +11,7 @@ application through the eventdev API.\n :maxdepth: 2\n :numbered:\n \n+ cnxk\n dlb2\n dpaa\n dpaa2\ndiff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c\nnew file mode 100644\nindex 000000000..b7f9c81bd\n--- /dev/null\n+++ b/drivers/event/cnxk/cnxk_eventdev.c\n@@ -0,0 +1,68 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell International Ltd.\n+ */\n+\n+#include \"cnxk_eventdev.h\"\n+\n+int\n+cnxk_sso_init(struct rte_eventdev *event_dev)\n+{\n+\tconst struct rte_memzone *mz = NULL;\n+\tstruct rte_pci_device *pci_dev;\n+\tstruct cnxk_sso_evdev *dev;\n+\tint rc;\n+\n+\tmz = rte_memzone_reserve(CNXK_SSO_MZ_NAME, sizeof(uint64_t),\n+\t\t\t\t SOCKET_ID_ANY, 0);\n+\tif (mz == NULL) {\n+\t\tplt_err(\"Failed to create eventdev memzone\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tdev = cnxk_sso_pmd_priv(event_dev);\n+\tpci_dev = container_of(event_dev->dev, struct rte_pci_device, device);\n+\tdev->sso.pci_dev = pci_dev;\n+\n+\t*(uint64_t *)mz->addr = (uint64_t)dev;\n+\n+\t/* Initialize the base cnxk_dev object */\n+\trc = roc_sso_dev_init(&dev->sso);\n+\tif (rc < 0) {\n+\t\tplt_err(\"Failed to initialize RoC SSO rc=%d\", rc);\n+\t\tgoto error;\n+\t}\n+\n+\tdev->is_timeout_deq = 0;\n+\tdev->min_dequeue_timeout_ns = USEC2NSEC(1);\n+\tdev->max_dequeue_timeout_ns = USEC2NSEC(0x3FF);\n+\tdev->max_num_events = -1;\n+\tdev->nb_event_queues = 0;\n+\tdev->nb_event_ports = 0;\n+\n+\treturn 0;\n+\n+error:\n+\trte_memzone_free(mz);\n+\treturn rc;\n+}\n+\n+int\n+cnxk_sso_fini(struct rte_eventdev *event_dev)\n+{\n+\tstruct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);\n+\n+\t/* For secondary processes, nothing to be done */\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n+\t\treturn 0;\n+\n+\troc_sso_rsrc_fini(&dev->sso);\n+\troc_sso_dev_fini(&dev->sso);\n+\n+\treturn 0;\n+}\n+\n+int\n+cnxk_sso_remove(struct rte_pci_device *pci_dev)\n+{\n+\treturn rte_event_pmd_pci_remove(pci_dev, cnxk_sso_fini);\n+}\ndiff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h\nnew file mode 100644\nindex 000000000..148b327a1\n--- /dev/null\n+++ b/drivers/event/cnxk/cnxk_eventdev.h\n@@ -0,0 +1,39 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell International Ltd.\n+ */\n+\n+#ifndef __CNXK_EVENTDEV_H__\n+#define __CNXK_EVENTDEV_H__\n+\n+#include <rte_pci.h>\n+\n+#include <eventdev_pmd_pci.h>\n+\n+#include \"roc_api.h\"\n+\n+#define USEC2NSEC(__us) ((__us)*1E3)\n+\n+#define CNXK_SSO_MZ_NAME \"cnxk_evdev_mz\"\n+\n+struct cnxk_sso_evdev {\n+\tstruct roc_sso sso;\n+\tuint8_t is_timeout_deq;\n+\tuint8_t nb_event_queues;\n+\tuint8_t nb_event_ports;\n+\tuint32_t min_dequeue_timeout_ns;\n+\tuint32_t max_dequeue_timeout_ns;\n+\tint32_t max_num_events;\n+} __rte_cache_aligned;\n+\n+static inline struct cnxk_sso_evdev *\n+cnxk_sso_pmd_priv(const struct rte_eventdev *event_dev)\n+{\n+\treturn event_dev->data->dev_private;\n+}\n+\n+/* Common ops API. */\n+int cnxk_sso_init(struct rte_eventdev *event_dev);\n+int cnxk_sso_fini(struct rte_eventdev *event_dev);\n+int cnxk_sso_remove(struct rte_pci_device *pci_dev);\n+\n+#endif /* __CNXK_EVENTDEV_H__ */\ndiff --git a/drivers/event/cnxk/meson.build b/drivers/event/cnxk/meson.build\nnew file mode 100644\nindex 000000000..e454dc863\n--- /dev/null\n+++ b/drivers/event/cnxk/meson.build\n@@ -0,0 +1,13 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(C) 2021 Marvell International Ltd.\n+#\n+\n+if not is_linux or not dpdk_conf.get('RTE_ARCH_64')\n+ build = false\n+ reason = 'only supported on 64-bit Linux'\n+ subdir_done()\n+endif\n+\n+sources = files('cnxk_eventdev.c')\n+\n+deps += ['bus_pci', 'common_cnxk', 'net_cnxk']\ndiff --git a/drivers/event/cnxk/version.map b/drivers/event/cnxk/version.map\nnew file mode 100644\nindex 000000000..ee80c5172\n--- /dev/null\n+++ b/drivers/event/cnxk/version.map\n@@ -0,0 +1,3 @@\n+INTERNAL {\n+\tlocal: *;\n+};\ndiff --git a/drivers/event/meson.build b/drivers/event/meson.build\nindex 539c5aeb9..63d6b410b 100644\n--- a/drivers/event/meson.build\n+++ b/drivers/event/meson.build\n@@ -6,6 +6,7 @@ if is_windows\n endif\n \n drivers = [\n+ 'cnxk',\n 'dlb2',\n 'dpaa',\n 'dpaa2',\n", "prefixes": [ "v2", "01/33" ] }