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GET /api/patches/92170/?format=api
{ "id": 92170, "url": "http://patches.dpdk.org/api/patches/92170/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/fceadab337b736c8ccde567c922c9842f2b8dd26.1619439044.git.sthotton@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<fceadab337b736c8ccde567c922c9842f2b8dd26.1619439044.git.sthotton@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/fceadab337b736c8ccde567c922c9842f2b8dd26.1619439044.git.sthotton@marvell.com", "date": "2021-04-26T12:21:06", "name": "[v2,1/2] event/octeontx2: fix crypto adapter queue pair ops", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "f5246ca924c6328a49beb46ac830a3489ae0208e", "submitter": { "id": 2049, "url": "http://patches.dpdk.org/api/people/2049/?format=api", "name": "Shijith Thotton", "email": "sthotton@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/fceadab337b736c8ccde567c922c9842f2b8dd26.1619439044.git.sthotton@marvell.com/mbox/", "series": [ { "id": 16673, "url": "http://patches.dpdk.org/api/series/16673/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16673", "date": "2021-04-26T12:21:05", "name": "event/octeontx2: fixes for crypto adapter", "version": 2, "mbox": "http://patches.dpdk.org/series/16673/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/92170/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/92170/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id ED286A0548;\n\tMon, 26 Apr 2021 14:21:36 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id AE9B4411C3;\n\tMon, 26 Apr 2021 14:21:31 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 74AE0411BB\n for <dev@dpdk.org>; Mon, 26 Apr 2021 14:21:30 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 13QCGYJW024308 for <dev@dpdk.org>; Mon, 26 Apr 2021 05:21:29 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 385hfr1s3b-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Mon, 26 Apr 2021 05:21:29 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Mon, 26 Apr 2021 05:21:27 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Mon, 26 Apr 2021 05:21:28 -0700", "from localhost.localdomain (unknown [10.28.34.29])\n by maili.marvell.com (Postfix) with ESMTP id D7F703F7040;\n Mon, 26 Apr 2021 05:21:25 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=NTB+zv9FtIw5jgsbRRg73SM6TRMEDZLJnMH7JtsfSvM=;\n b=lNGiEBO2osAyygDJL1wuErkGmiP4C/dGn1bKfMo9hHzDnTX4qRYemm0aC5K2es3hhTkR\n bLYpwk5bTOASZOLbBhpIuekHOd9j/4H6+Np0SUYBy9V5Ky+4CjduflFWx3C2XN9aheay\n 3SW/MUvaiIp7ZEkwNft+6Ko99BomhxiwjKrdguixZdKqSupBjCu2vfXZYAKrhYxKWYuH\n 6It7qbRYkD9W97Hzrmu518/KgmPI0mFI2zk5bYrIfczqkjIMp680GDRjZhGcY+XrkbCy\n 95iEs9mTfNlU9t19P3PqT8N5+Snd6tzrjY/4qfZm67uohuvFDJR01gR2LR+ZF/V+lK+4 4w==", "From": "Shijith Thotton <sthotton@marvell.com>", "To": "<dev@dpdk.org>", "CC": "Shijith Thotton <sthotton@marvell.com>, Jerin Jacob <jerinj@marvell.com>,\n Anoob Joseph <anoobj@marvell.com>, Ankur Dwivedi <adwivedi@marvell.com>,\n Pavan Nikhilesh <pbhagavatula@marvell.com>", "Date": "Mon, 26 Apr 2021 17:51:06 +0530", "Message-ID": "\n <fceadab337b736c8ccde567c922c9842f2b8dd26.1619439044.git.sthotton@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<cover.1619439044.git.sthotton@marvell.com>", "References": "<cover.1618513149.git.sthotton@marvell.com>\n <cover.1619439044.git.sthotton@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "0lebT_60TxXSTNiHNWj9N3CRwhmt91Dn", "X-Proofpoint-GUID": "0lebT_60TxXSTNiHNWj9N3CRwhmt91Dn", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761\n definitions=2021-04-26_05:2021-04-26,\n 2021-04-26 signatures=0", "Subject": "[dpdk-dev] [PATCH v2 1/2] event/octeontx2: fix crypto adapter queue\n pair ops", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Parameter queue_pair_id of crypto adapter queue pair add/del operation\ncan be -1 to select all pre configured crypto queue pairs. Added support\nfor the same in driver. Also added a member in cpt qp structure to\nindicate binding state of a queue pair to an event queue.\n\nFixes: 29768f78d5a7 (\"event/octeontx2: add crypto adapter framework\")\n\nSigned-off-by: Shijith Thotton <sthotton@marvell.com>\n---\n drivers/crypto/octeontx2/otx2_cryptodev_qp.h | 4 +-\n .../event/octeontx2/otx2_evdev_crypto_adptr.c | 102 ++++++++++++------\n 2 files changed, 75 insertions(+), 31 deletions(-)", "diff": "diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_qp.h b/drivers/crypto/octeontx2/otx2_cryptodev_qp.h\nindex 189fa3db4..95bce3621 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_qp.h\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_qp.h\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright (C) 2020 Marvell International Ltd.\n+ * Copyright (C) 2020-2021 Marvell.\n */\n \n #ifndef _OTX2_CRYPTODEV_QP_H_\n@@ -39,6 +39,8 @@ struct otx2_cpt_qp {\n \t */\n \tuint8_t ca_enable;\n \t/**< Set when queue pair is added to crypto adapter */\n+\tuint8_t qp_ev_bind;\n+\t/**< Set when queue pair is bound to event queue */\n };\n \n #endif /* _OTX2_CRYPTODEV_QP_H_ */\ndiff --git a/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c b/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c\nindex 2c9b347f0..ed600a659 100644\n--- a/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c\n+++ b/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c\n@@ -1,10 +1,11 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright (C) 2020 Marvell International Ltd.\n+ * Copyright (C) 2020-2021 Marvell.\n */\n \n #include <rte_cryptodev.h>\n #include <rte_eventdev.h>\n \n+#include \"otx2_cryptodev.h\"\n #include \"otx2_cryptodev_hw_access.h\"\n #include \"otx2_cryptodev_qp.h\"\n #include \"otx2_cryptodev_mbox.h\"\n@@ -24,30 +25,66 @@ otx2_ca_caps_get(const struct rte_eventdev *dev,\n \treturn 0;\n }\n \n-int\n-otx2_ca_qp_add(const struct rte_eventdev *dev, const struct rte_cryptodev *cdev,\n-\t\tint32_t queue_pair_id, const struct rte_event *event)\n+static int\n+otx2_ca_qp_sso_link(const struct rte_cryptodev *cdev, struct otx2_cpt_qp *qp,\n+\t\t uint16_t sso_pf_func)\n {\n-\tstruct otx2_sso_evdev *sso_evdev = sso_pmd_priv(dev);\n \tunion otx2_cpt_af_lf_ctl2 af_lf_ctl2;\n-\tstruct otx2_cpt_qp *qp;\n \tint ret;\n \n-\tqp = cdev->data->queue_pairs[queue_pair_id];\n-\n-\tqp->ca_enable = 1;\n-\trte_memcpy(&qp->ev, event, sizeof(struct rte_event));\n-\n \tret = otx2_cpt_af_reg_read(cdev, OTX2_CPT_AF_LF_CTL2(qp->id),\n-\t\t\tqp->blkaddr, &af_lf_ctl2.u);\n+\t\t\t\t qp->blkaddr, &af_lf_ctl2.u);\n \tif (ret)\n \t\treturn ret;\n \n-\taf_lf_ctl2.s.sso_pf_func = otx2_sso_pf_func_get();\n+\taf_lf_ctl2.s.sso_pf_func = sso_pf_func;\n \tret = otx2_cpt_af_reg_write(cdev, OTX2_CPT_AF_LF_CTL2(qp->id),\n-\t\t\tqp->blkaddr, af_lf_ctl2.u);\n-\tif (ret)\n-\t\treturn ret;\n+\t\t\t\t qp->blkaddr, af_lf_ctl2.u);\n+\treturn ret;\n+}\n+\n+static void\n+otx2_ca_qp_init(struct otx2_cpt_qp *qp, const struct rte_event *event)\n+{\n+\tif (event) {\n+\t\tqp->qp_ev_bind = 1;\n+\t\trte_memcpy(&qp->ev, event, sizeof(struct rte_event));\n+\t} else {\n+\t\tqp->qp_ev_bind = 0;\n+\t}\n+\tqp->ca_enable = 1;\n+}\n+\n+int\n+otx2_ca_qp_add(const struct rte_eventdev *dev, const struct rte_cryptodev *cdev,\n+\t\tint32_t queue_pair_id, const struct rte_event *event)\n+{\n+\tstruct otx2_sso_evdev *sso_evdev = sso_pmd_priv(dev);\n+\tstruct otx2_cpt_vf *vf = cdev->data->dev_private;\n+\tuint16_t sso_pf_func = otx2_sso_pf_func_get();\n+\tstruct otx2_cpt_qp *qp;\n+\tuint8_t qp_id;\n+\tint ret;\n+\n+\tif (queue_pair_id == -1) {\n+\t\tfor (qp_id = 0; qp_id < vf->nb_queues; qp_id++) {\n+\t\t\tqp = cdev->data->queue_pairs[qp_id];\n+\t\t\tret = otx2_ca_qp_sso_link(cdev, qp, sso_pf_func);\n+\t\t\tif (ret) {\n+\t\t\t\tuint8_t qp_tmp;\n+\t\t\t\tfor (qp_tmp = 0; qp_tmp < qp_id; qp_tmp++)\n+\t\t\t\t\totx2_ca_qp_del(dev, cdev, qp_tmp);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\t\t\totx2_ca_qp_init(qp, event);\n+\t\t}\n+\t} else {\n+\t\tqp = cdev->data->queue_pairs[queue_pair_id];\n+\t\tret = otx2_ca_qp_sso_link(cdev, qp, sso_pf_func);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t\totx2_ca_qp_init(qp, event);\n+\t}\n \n \tsso_evdev->rx_offloads |= NIX_RX_OFFLOAD_SECURITY_F;\n \tsso_fastpath_fns_set((struct rte_eventdev *)(uintptr_t)dev);\n@@ -59,24 +96,29 @@ int\n otx2_ca_qp_del(const struct rte_eventdev *dev, const struct rte_cryptodev *cdev,\n \t\tint32_t queue_pair_id)\n {\n-\tunion otx2_cpt_af_lf_ctl2 af_lf_ctl2;\n+\tstruct otx2_cpt_vf *vf = cdev->data->dev_private;\n \tstruct otx2_cpt_qp *qp;\n+\tuint8_t qp_id;\n \tint ret;\n \n \tRTE_SET_USED(dev);\n \n-\tqp = cdev->data->queue_pairs[queue_pair_id];\n-\tqp->ca_enable = 0;\n-\tmemset(&qp->ev, 0, sizeof(struct rte_event));\n+\tret = 0;\n+\tif (queue_pair_id == -1) {\n+\t\tfor (qp_id = 0; qp_id < vf->nb_queues; qp_id++) {\n+\t\t\tqp = cdev->data->queue_pairs[qp_id];\n+\t\t\tret = otx2_ca_qp_sso_link(cdev, qp, 0);\n+\t\t\tif (ret)\n+\t\t\t\treturn ret;\n+\t\t\tqp->ca_enable = 0;\n+\t\t}\n+\t} else {\n+\t\tqp = cdev->data->queue_pairs[queue_pair_id];\n+\t\tret = otx2_ca_qp_sso_link(cdev, qp, 0);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t\tqp->ca_enable = 0;\n+\t}\n \n-\tret = otx2_cpt_af_reg_read(cdev, OTX2_CPT_AF_LF_CTL2(qp->id),\n-\t\t\tqp->blkaddr, &af_lf_ctl2.u);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\taf_lf_ctl2.s.sso_pf_func = 0;\n-\tret = otx2_cpt_af_reg_write(cdev, OTX2_CPT_AF_LF_CTL2(qp->id),\n-\t\t\tqp->blkaddr, af_lf_ctl2.u);\n-\n-\treturn ret;\n+\treturn 0;\n }\n", "prefixes": [ "v2", "1/2" ] }