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{
    "id": 92056,
    "url": "http://patches.dpdk.org/api/patches/92056/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210423074203.948915-1-yuying.zhang@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20210423074203.948915-1-yuying.zhang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20210423074203.948915-1-yuying.zhang@intel.com",
    "date": "2021-04-23T07:42:02",
    "name": "[v2,1/2] net/ice: refactor input set fields for switch filter",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "6e3a4d81dc286d628b869ddc663301bfe8fa4082",
    "submitter": {
        "id": 1844,
        "url": "http://patches.dpdk.org/api/people/1844/?format=api",
        "name": "Zhang, Yuying",
        "email": "yuying.zhang@intel.com"
    },
    "delegate": {
        "id": 1540,
        "url": "http://patches.dpdk.org/api/users/1540/?format=api",
        "username": "qzhan15",
        "first_name": "Qi",
        "last_name": "Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210423074203.948915-1-yuying.zhang@intel.com/mbox/",
    "series": [
        {
            "id": 16621,
            "url": "http://patches.dpdk.org/api/series/16621/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16621",
            "date": "2021-04-23T07:42:02",
            "name": "[v2,1/2] net/ice: refactor input set fields for switch filter",
            "version": 2,
            "mbox": "http://patches.dpdk.org/series/16621/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/92056/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/92056/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 161AAA0548;\n\tFri, 23 Apr 2021 09:53:17 +0200 (CEST)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id CAA604067E;\n\tFri, 23 Apr 2021 09:53:16 +0200 (CEST)",
            "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n by mails.dpdk.org (Postfix) with ESMTP id 62FDF4014F\n for <dev@dpdk.org>; Fri, 23 Apr 2021 09:53:14 +0200 (CEST)",
            "from fmsmga002.fm.intel.com ([10.253.24.26])\n by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 23 Apr 2021 00:53:12 -0700",
            "from dpdk-yyzhang2.sh.intel.com ([10.67.117.129])\n by fmsmga002.fm.intel.com with ESMTP; 23 Apr 2021 00:53:09 -0700"
        ],
        "IronPort-SDR": [
            "\n M7goQViWEJYl7IW3tu3Hk1EsxWJSidZGC/wymIcyeo67zINrDoEfG/VDAbqt0NcfjC5/rVL2Gu\n 7zaF8GSnpaUQ==",
            "\n mAGETLgMNV6j2BuAP8I0At2fcQwcxKepQ3TiGNjNajwWktisSMlhOsrPZ+nzx3nSrV1QXsTIWY\n SemwfJfurTWQ=="
        ],
        "X-IronPort-AV": [
            "E=McAfee;i=\"6200,9189,9962\"; a=\"281360786\"",
            "E=Sophos;i=\"5.82,245,1613462400\"; d=\"scan'208\";a=\"281360786\"",
            "E=Sophos;i=\"5.82,245,1613462400\"; d=\"scan'208\";a=\"456127562\""
        ],
        "X-ExtLoop1": "1",
        "From": "Yuying Zhang <yuying.zhang@intel.com>",
        "To": "dev@dpdk.org,\n\tqi.z.zhang@intel.com,\n\thaiyue.wang@intel.com",
        "Cc": "junfeng.guo@intel.com, Zhirun.Yan@intel.com,\n Yuying Zhang <yuying.zhang@intel.com>",
        "Date": "Fri, 23 Apr 2021 07:42:02 +0000",
        "Message-Id": "<20210423074203.948915-1-yuying.zhang@intel.com>",
        "X-Mailer": "git-send-email 2.25.1",
        "In-Reply-To": "<20210422100541.935478-1-yuying.zhang@intel.com>",
        "References": "<20210422100541.935478-1-yuying.zhang@intel.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Subject": "[dpdk-dev] [PATCH v2 1/2] net/ice: refactor input set fields for\n switch filter",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Input set has been divided into inner and outer part to distinguish\ndifferent fields. However, the parse method of switch filter doesn't\nmatch this update. Refactor switch filter to distingush inner and outer\ninput set in the same way as other filters.\n\nSigned-off-by: Yuying Zhang <yuying.zhang@intel.com>\n---\n drivers/net/ice/ice_switch_filter.c | 782 ++++++++++++----------------\n 1 file changed, 341 insertions(+), 441 deletions(-)",
    "diff": "diff --git a/drivers/net/ice/ice_switch_filter.c b/drivers/net/ice/ice_switch_filter.c\nindex 0493e4dee2..c9d2ec7410 100644\n--- a/drivers/net/ice/ice_switch_filter.c\n+++ b/drivers/net/ice/ice_switch_filter.c\n@@ -35,8 +35,7 @@\n #define ICE_SW_INSET_ETHER ( \\\n \tICE_INSET_DMAC | ICE_INSET_SMAC | ICE_INSET_ETHERTYPE)\n #define ICE_SW_INSET_MAC_VLAN ( \\\n-\tICE_INSET_DMAC | ICE_INSET_SMAC | ICE_INSET_ETHERTYPE | \\\n-\tICE_INSET_VLAN_INNER)\n+\tICE_SW_INSET_ETHER | ICE_INSET_VLAN_INNER)\n #define ICE_SW_INSET_MAC_QINQ  ( \\\n \tICE_INSET_DMAC | ICE_INSET_SMAC | ICE_INSET_VLAN_INNER | \\\n \tICE_INSET_VLAN_OUTER)\n@@ -68,38 +67,38 @@\n \tICE_INSET_IPV6_HOP_LIMIT | ICE_INSET_IPV6_TC | \\\n \tICE_INSET_UDP_DST_PORT | ICE_INSET_UDP_SRC_PORT)\n #define ICE_SW_INSET_DIST_NVGRE_IPV4 ( \\\n-\tICE_INSET_TUN_IPV4_SRC | ICE_INSET_TUN_IPV4_DST | \\\n-\tICE_INSET_TUN_DMAC | ICE_INSET_TUN_NVGRE_TNI | ICE_INSET_IPV4_DST)\n+\tICE_INSET_IPV4_SRC | ICE_INSET_IPV4_DST | ICE_INSET_DMAC | \\\n+\tICE_INSET_TUN_NVGRE_TNI)\n #define ICE_SW_INSET_DIST_VXLAN_IPV4 ( \\\n-\tICE_INSET_TUN_IPV4_SRC | ICE_INSET_TUN_IPV4_DST | \\\n-\tICE_INSET_TUN_DMAC | ICE_INSET_TUN_VXLAN_VNI | ICE_INSET_IPV4_DST)\n+\tICE_INSET_IPV4_SRC | ICE_INSET_IPV4_DST | ICE_INSET_DMAC | \\\n+\tICE_INSET_TUN_VXLAN_VNI)\n #define ICE_SW_INSET_DIST_NVGRE_IPV4_TCP ( \\\n-\tICE_INSET_TUN_IPV4_SRC | ICE_INSET_TUN_IPV4_DST | \\\n-\tICE_INSET_TUN_TCP_SRC_PORT | ICE_INSET_TUN_TCP_DST_PORT | \\\n-\tICE_INSET_TUN_DMAC | ICE_INSET_TUN_NVGRE_TNI | ICE_INSET_IPV4_DST)\n+\tICE_INSET_IPV4_SRC | ICE_INSET_IPV4_DST | \\\n+\tICE_INSET_TCP_SRC_PORT | ICE_INSET_TCP_DST_PORT | \\\n+\tICE_INSET_DMAC | ICE_INSET_TUN_NVGRE_TNI)\n #define ICE_SW_INSET_DIST_NVGRE_IPV4_UDP ( \\\n-\tICE_INSET_TUN_IPV4_SRC | ICE_INSET_TUN_IPV4_DST | \\\n-\tICE_INSET_TUN_UDP_SRC_PORT | ICE_INSET_TUN_UDP_DST_PORT | \\\n-\tICE_INSET_TUN_DMAC | ICE_INSET_TUN_NVGRE_TNI | ICE_INSET_IPV4_DST)\n+\tICE_INSET_IPV4_SRC | ICE_INSET_IPV4_DST | \\\n+\tICE_INSET_UDP_SRC_PORT | ICE_INSET_UDP_DST_PORT | \\\n+\tICE_INSET_DMAC | ICE_INSET_TUN_NVGRE_TNI)\n #define ICE_SW_INSET_DIST_VXLAN_IPV4_TCP ( \\\n-\tICE_INSET_TUN_IPV4_SRC | ICE_INSET_TUN_IPV4_DST | \\\n-\tICE_INSET_TUN_TCP_SRC_PORT | ICE_INSET_TUN_TCP_DST_PORT | \\\n-\tICE_INSET_TUN_DMAC | ICE_INSET_TUN_VXLAN_VNI | ICE_INSET_IPV4_DST)\n+\tICE_INSET_IPV4_SRC | ICE_INSET_IPV4_DST | \\\n+\tICE_INSET_TCP_SRC_PORT | ICE_INSET_TCP_DST_PORT | \\\n+\tICE_INSET_DMAC | ICE_INSET_TUN_VXLAN_VNI)\n #define ICE_SW_INSET_DIST_VXLAN_IPV4_UDP ( \\\n-\tICE_INSET_TUN_IPV4_SRC | ICE_INSET_TUN_IPV4_DST | \\\n-\tICE_INSET_TUN_UDP_SRC_PORT | ICE_INSET_TUN_UDP_DST_PORT | \\\n-\tICE_INSET_TUN_DMAC | ICE_INSET_TUN_VXLAN_VNI | ICE_INSET_IPV4_DST)\n+\tICE_INSET_IPV4_SRC | ICE_INSET_IPV4_DST | \\\n+\tICE_INSET_UDP_SRC_PORT | ICE_INSET_UDP_DST_PORT | \\\n+\tICE_INSET_DMAC | ICE_INSET_TUN_VXLAN_VNI)\n #define ICE_SW_INSET_PERM_TUNNEL_IPV4 ( \\\n-\tICE_INSET_TUN_IPV4_SRC | ICE_INSET_TUN_IPV4_DST | \\\n-\tICE_INSET_TUN_IPV4_PROTO | ICE_INSET_TUN_IPV4_TOS)\n+\tICE_INSET_IPV4_SRC | ICE_INSET_IPV4_DST | \\\n+\tICE_INSET_IPV4_PROTO | ICE_INSET_IPV4_TOS)\n #define ICE_SW_INSET_PERM_TUNNEL_IPV4_TCP ( \\\n-\tICE_INSET_TUN_IPV4_SRC | ICE_INSET_TUN_IPV4_DST | \\\n-\tICE_INSET_TUN_TCP_SRC_PORT | ICE_INSET_TUN_TCP_DST_PORT | \\\n-\tICE_INSET_TUN_IPV4_TOS)\n+\tICE_INSET_IPV4_SRC | ICE_INSET_IPV4_DST | \\\n+\tICE_INSET_TCP_SRC_PORT | ICE_INSET_TCP_DST_PORT | \\\n+\tICE_INSET_IPV4_TOS)\n #define ICE_SW_INSET_PERM_TUNNEL_IPV4_UDP ( \\\n-\tICE_INSET_TUN_IPV4_SRC | ICE_INSET_TUN_IPV4_DST | \\\n-\tICE_INSET_TUN_UDP_SRC_PORT | ICE_INSET_TUN_UDP_DST_PORT | \\\n-\tICE_INSET_TUN_IPV4_TOS)\n+\tICE_INSET_IPV4_SRC | ICE_INSET_IPV4_DST | \\\n+\tICE_INSET_UDP_SRC_PORT | ICE_INSET_UDP_DST_PORT | \\\n+\tICE_INSET_IPV4_TOS)\n #define ICE_SW_INSET_MAC_PPPOE  ( \\\n \tICE_INSET_VLAN_OUTER | ICE_INSET_VLAN_INNER | \\\n \tICE_INSET_DMAC | ICE_INSET_ETHERTYPE | ICE_INSET_PPPOE_SESSION)\n@@ -141,74 +140,26 @@\n \tICE_SW_INSET_MAC_IPV4 | ICE_INSET_GTPU_TEID)\n #define ICE_SW_INSET_MAC_IPV6_GTPU ( \\\n \tICE_SW_INSET_MAC_IPV6 | ICE_INSET_GTPU_TEID)\n-#define ICE_SW_INSET_MAC_IPV4_GTPU_IPV4 ( \\\n-\tICE_INSET_DMAC | ICE_INSET_GTPU_TEID | \\\n-\tICE_INSET_TUN_IPV4_SRC | ICE_INSET_TUN_IPV4_DST)\n-#define ICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV4 ( \\\n-\tICE_SW_INSET_MAC_IPV4_GTPU_IPV4 | ICE_INSET_GTPU_QFI)\n-#define ICE_SW_INSET_MAC_IPV4_GTPU_IPV6 ( \\\n-\tICE_INSET_DMAC | ICE_INSET_GTPU_TEID | \\\n-\tICE_INSET_TUN_IPV6_SRC | ICE_INSET_TUN_IPV6_DST)\n-#define ICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV6 ( \\\n-\tICE_SW_INSET_MAC_IPV4_GTPU_IPV6 | ICE_INSET_GTPU_QFI)\n-#define ICE_SW_INSET_MAC_IPV6_GTPU_IPV4 ( \\\n-\tICE_INSET_DMAC | ICE_INSET_GTPU_TEID | \\\n-\tICE_INSET_TUN_IPV4_SRC | ICE_INSET_TUN_IPV4_DST)\n-#define ICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV4 ( \\\n-\tICE_SW_INSET_MAC_IPV6_GTPU_IPV4 | ICE_INSET_GTPU_QFI)\n-#define ICE_SW_INSET_MAC_IPV6_GTPU_IPV6 ( \\\n-\tICE_INSET_DMAC | ICE_INSET_GTPU_TEID | \\\n-\tICE_INSET_TUN_IPV6_SRC | ICE_INSET_TUN_IPV6_DST)\n-#define ICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV6 ( \\\n-\tICE_SW_INSET_MAC_IPV6_GTPU_IPV6 | ICE_INSET_GTPU_QFI)\n-#define ICE_SW_INSET_MAC_IPV4_GTPU_IPV4_UDP ( \\\n-\tICE_SW_INSET_MAC_IPV4_GTPU_IPV4 | \\\n-\tICE_INSET_TUN_UDP_SRC_PORT | ICE_INSET_TUN_UDP_DST_PORT)\n-#define ICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV4_UDP ( \\\n-\tICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV4 | \\\n-\tICE_INSET_TUN_UDP_SRC_PORT | ICE_INSET_TUN_UDP_DST_PORT)\n-#define ICE_SW_INSET_MAC_IPV4_GTPU_IPV4_TCP ( \\\n-\tICE_SW_INSET_MAC_IPV4_GTPU_IPV4 | \\\n-\tICE_INSET_TUN_TCP_SRC_PORT | ICE_INSET_TUN_TCP_DST_PORT)\n-#define ICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV4_TCP ( \\\n-\tICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV4 | \\\n-\tICE_INSET_TUN_TCP_SRC_PORT | ICE_INSET_TUN_TCP_DST_PORT)\n-#define ICE_SW_INSET_MAC_IPV4_GTPU_IPV6_UDP ( \\\n-\tICE_SW_INSET_MAC_IPV4_GTPU_IPV6 | \\\n-\tICE_INSET_TUN_UDP_SRC_PORT | ICE_INSET_TUN_UDP_DST_PORT)\n-#define ICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV6_UDP ( \\\n-\tICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV6 | \\\n-\tICE_INSET_TUN_UDP_SRC_PORT | ICE_INSET_TUN_UDP_DST_PORT)\n-#define ICE_SW_INSET_MAC_IPV4_GTPU_IPV6_TCP ( \\\n-\tICE_SW_INSET_MAC_IPV4_GTPU_IPV6 | \\\n-\tICE_INSET_TUN_TCP_SRC_PORT | ICE_INSET_TUN_TCP_DST_PORT)\n-#define ICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV6_TCP ( \\\n-\tICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV6 | \\\n-\tICE_INSET_TUN_TCP_SRC_PORT | ICE_INSET_TUN_TCP_DST_PORT)\n-#define ICE_SW_INSET_MAC_IPV6_GTPU_IPV4_UDP ( \\\n-\tICE_SW_INSET_MAC_IPV6_GTPU_IPV4 | \\\n-\tICE_INSET_TUN_UDP_SRC_PORT | ICE_INSET_TUN_UDP_DST_PORT)\n-#define ICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV4_UDP ( \\\n-\tICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV4 | \\\n-\tICE_INSET_TUN_UDP_SRC_PORT | ICE_INSET_TUN_UDP_DST_PORT)\n-#define ICE_SW_INSET_MAC_IPV6_GTPU_IPV4_TCP ( \\\n-\tICE_SW_INSET_MAC_IPV6_GTPU_IPV4 | \\\n-\tICE_INSET_TUN_TCP_SRC_PORT | ICE_INSET_TUN_TCP_DST_PORT)\n-#define ICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV4_TCP ( \\\n-\tICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV4 | \\\n-\tICE_INSET_TUN_TCP_SRC_PORT | ICE_INSET_TUN_TCP_DST_PORT)\n-#define ICE_SW_INSET_MAC_IPV6_GTPU_IPV6_UDP ( \\\n-\tICE_SW_INSET_MAC_IPV6_GTPU_IPV6 | \\\n-\tICE_INSET_TUN_UDP_SRC_PORT | ICE_INSET_TUN_UDP_DST_PORT)\n-#define ICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV6_UDP ( \\\n-\tICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV6 | \\\n-\tICE_INSET_TUN_UDP_SRC_PORT | ICE_INSET_TUN_UDP_DST_PORT)\n-#define ICE_SW_INSET_MAC_IPV6_GTPU_IPV6_TCP ( \\\n-\tICE_SW_INSET_MAC_IPV6_GTPU_IPV6 | \\\n-\tICE_INSET_TUN_TCP_SRC_PORT | ICE_INSET_TUN_TCP_DST_PORT)\n-#define ICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV6_TCP ( \\\n-\tICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV6 | \\\n-\tICE_INSET_TUN_TCP_SRC_PORT | ICE_INSET_TUN_TCP_DST_PORT)\n+#define ICE_SW_INSET_MAC_GTPU_OUTER ( \\\n+\tICE_INSET_DMAC | ICE_INSET_GTPU_TEID)\n+#define ICE_SW_INSET_MAC_GTPU_EH_OUTER ( \\\n+\tICE_SW_INSET_MAC_GTPU_OUTER | ICE_INSET_GTPU_QFI)\n+#define ICE_SW_INSET_GTPU_IPV4 ( \\\n+\tICE_INSET_IPV4_SRC | ICE_INSET_IPV4_DST)\n+#define ICE_SW_INSET_GTPU_IPV6 ( \\\n+\tICE_INSET_IPV6_SRC | ICE_INSET_IPV6_DST)\n+#define ICE_SW_INSET_GTPU_IPV4_UDP ( \\\n+\tICE_SW_INSET_GTPU_IPV4 | ICE_INSET_UDP_SRC_PORT | \\\n+\tICE_INSET_UDP_DST_PORT)\n+#define ICE_SW_INSET_GTPU_IPV4_TCP ( \\\n+\tICE_SW_INSET_GTPU_IPV4 | ICE_INSET_TCP_SRC_PORT | \\\n+\tICE_INSET_TCP_DST_PORT)\n+#define ICE_SW_INSET_GTPU_IPV6_UDP ( \\\n+\tICE_SW_INSET_GTPU_IPV6 | ICE_INSET_UDP_SRC_PORT | \\\n+\tICE_INSET_UDP_DST_PORT)\n+#define ICE_SW_INSET_GTPU_IPV6_TCP ( \\\n+\tICE_SW_INSET_GTPU_IPV6 | ICE_INSET_TCP_SRC_PORT | \\\n+\tICE_INSET_TCP_DST_PORT)\n \n struct sw_meta {\n \tstruct ice_adv_lkup_elem *list;\n@@ -221,160 +172,160 @@ static struct ice_flow_parser ice_switch_perm_parser;\n \n static struct\n ice_pattern_match_item ice_switch_pattern_dist_list[] = {\n-\t{pattern_ethertype,\t\t\t\tICE_SW_INSET_ETHER,\t\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_ethertype_vlan,\t\t\tICE_SW_INSET_MAC_VLAN,\t\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_ethertype_qinq,\t\t\tICE_SW_INSET_MAC_QINQ,\t\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_arp,\t\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4,\t\t\t\tICE_SW_INSET_MAC_IPV4,\t\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_udp,\t\t\t\tICE_SW_INSET_MAC_IPV4_UDP,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_tcp,\t\t\t\tICE_SW_INSET_MAC_IPV4_TCP,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6,\t\t\t\tICE_SW_INSET_MAC_IPV6,\t\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6_udp,\t\t\t\tICE_SW_INSET_MAC_IPV6_UDP,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6_tcp,\t\t\t\tICE_SW_INSET_MAC_IPV6_TCP,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_udp_vxlan_eth_ipv4,\t\tICE_SW_INSET_DIST_VXLAN_IPV4,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_udp_vxlan_eth_ipv4_udp,\tICE_SW_INSET_DIST_VXLAN_IPV4_UDP,\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_udp_vxlan_eth_ipv4_tcp,\tICE_SW_INSET_DIST_VXLAN_IPV4_TCP,\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_nvgre_eth_ipv4,\t\tICE_SW_INSET_DIST_NVGRE_IPV4,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_nvgre_eth_ipv4_udp,\t\tICE_SW_INSET_DIST_NVGRE_IPV4_UDP,\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_nvgre_eth_ipv4_tcp,\t\tICE_SW_INSET_DIST_NVGRE_IPV4_TCP,\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_pppoes,\t\t\t\tICE_SW_INSET_MAC_PPPOE,\t\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_vlan_pppoes,\t\t\tICE_SW_INSET_MAC_PPPOE,\t\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_pppoes_proto,\t\t\tICE_SW_INSET_MAC_PPPOE_PROTO,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_vlan_pppoes_proto,\t\t\tICE_SW_INSET_MAC_PPPOE_PROTO,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_pppoes_ipv4,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV4,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_pppoes_ipv4_tcp,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV4_TCP,\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_pppoes_ipv4_udp,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV4_UDP,\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_pppoes_ipv6,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV6,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_pppoes_ipv6_tcp,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV6_TCP,\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_pppoes_ipv6_udp,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV6_UDP,\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_vlan_pppoes_ipv4,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV4,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_vlan_pppoes_ipv4_tcp,\t\tICE_SW_INSET_MAC_PPPOE_IPV4_TCP,\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_vlan_pppoes_ipv4_udp,\t\tICE_SW_INSET_MAC_PPPOE_IPV4_UDP,\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_vlan_pppoes_ipv6,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV6,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_vlan_pppoes_ipv6_tcp,\t\tICE_SW_INSET_MAC_PPPOE_IPV6_TCP,\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_vlan_pppoes_ipv6_udp,\t\tICE_SW_INSET_MAC_PPPOE_IPV6_UDP,\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_esp,\t\t\t\tICE_SW_INSET_MAC_IPV4_ESP,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_udp_esp,\t\t\tICE_SW_INSET_MAC_IPV4_ESP,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6_esp,\t\t\t\tICE_SW_INSET_MAC_IPV6_ESP,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6_udp_esp,\t\t\tICE_SW_INSET_MAC_IPV6_ESP,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_ah,\t\t\t\tICE_SW_INSET_MAC_IPV4_AH,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6_ah,\t\t\t\tICE_SW_INSET_MAC_IPV6_AH,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6_udp_ah,\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_l2tp,\t\t\t\tICE_SW_INSET_MAC_IPV4_L2TP,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6_l2tp,\t\t\t\tICE_SW_INSET_MAC_IPV6_L2TP,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_pfcp,\t\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6_pfcp,\t\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_qinq_ipv4,\t\t\t\tICE_SW_INSET_MAC_QINQ_IPV4,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_qinq_ipv6,\t\t\t\tICE_SW_INSET_MAC_QINQ_IPV6,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_qinq_pppoes,\t\t\tICE_SW_INSET_MAC_PPPOE,\t\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_qinq_pppoes_proto,\t\t\tICE_SW_INSET_MAC_PPPOE_PROTO,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_qinq_pppoes_ipv4,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV4,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_qinq_pppoes_ipv6,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV6,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu,\t\t\t\tICE_SW_INSET_MAC_IPV4_GTPU,\t\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu,\t\t\t\tICE_SW_INSET_MAC_IPV6_GTPU,\t\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu_ipv4,\t\t\tICE_SW_INSET_MAC_IPV4_GTPU_IPV4,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu_eh_ipv4,\t\t\tICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV4,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu_ipv4_udp,\t\tICE_SW_INSET_MAC_IPV4_GTPU_IPV4_UDP,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu_eh_ipv4_udp,\t\tICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV4_UDP,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu_ipv4_tcp,\t\tICE_SW_INSET_MAC_IPV4_GTPU_IPV4_TCP,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu_eh_ipv4_tcp,\t\tICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV4_TCP,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu_ipv6,\t\t\tICE_SW_INSET_MAC_IPV4_GTPU_IPV6,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu_eh_ipv6,\t\t\tICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV6,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu_ipv6_udp,\t\tICE_SW_INSET_MAC_IPV4_GTPU_IPV6_UDP,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu_eh_ipv6_udp,\t\tICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV6_UDP,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu_ipv6_tcp,\t\tICE_SW_INSET_MAC_IPV4_GTPU_IPV6_TCP,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu_eh_ipv6_tcp,\t\tICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV6_TCP,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu_ipv4,\t\t\tICE_SW_INSET_MAC_IPV6_GTPU_IPV4,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu_eh_ipv4,\t\t\tICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV4,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu_ipv4_udp,\t\tICE_SW_INSET_MAC_IPV6_GTPU_IPV4_UDP,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu_eh_ipv4_udp,\t\tICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV4_UDP,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu_ipv4_tcp,\t\tICE_SW_INSET_MAC_IPV6_GTPU_IPV4_TCP,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu_eh_ipv4_tcp,\t\tICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV4_TCP,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu_ipv6,\t\t\tICE_SW_INSET_MAC_IPV6_GTPU_IPV6,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu_eh_ipv6,\t\t\tICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV6,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu_ipv6_udp,\t\tICE_SW_INSET_MAC_IPV6_GTPU_IPV6_UDP,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu_eh_ipv6_udp,\t\tICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV6_UDP,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu_ipv6_tcp,\t\tICE_SW_INSET_MAC_IPV6_GTPU_IPV6_UDP,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu_eh_ipv6_tcp,\t\tICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV6_TCP,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_ethertype,\t\t\t\tICE_SW_INSET_ETHER,\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_ethertype_vlan,\t\t\tICE_SW_INSET_MAC_VLAN,\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_ethertype_qinq,\t\t\tICE_SW_INSET_MAC_QINQ,\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_arp,\t\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4,\t\t\t\tICE_SW_INSET_MAC_IPV4,\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_udp,\t\t\t\tICE_SW_INSET_MAC_IPV4_UDP,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_tcp,\t\t\t\tICE_SW_INSET_MAC_IPV4_TCP,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6,\t\t\t\tICE_SW_INSET_MAC_IPV6,\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_udp,\t\t\t\tICE_SW_INSET_MAC_IPV6_UDP,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_tcp,\t\t\t\tICE_SW_INSET_MAC_IPV6_TCP,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_udp_vxlan_eth_ipv4,\t\tICE_INSET_IPV4_DST,\t\t\tICE_SW_INSET_DIST_VXLAN_IPV4,\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_udp_vxlan_eth_ipv4_udp,\tICE_INSET_IPV4_DST,\t\t\tICE_SW_INSET_DIST_VXLAN_IPV4_UDP,\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_udp_vxlan_eth_ipv4_tcp,\tICE_INSET_IPV4_DST,\t\t\tICE_SW_INSET_DIST_VXLAN_IPV4_TCP,\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_nvgre_eth_ipv4,\t\tICE_INSET_IPV4_DST,\t\t\tICE_SW_INSET_DIST_NVGRE_IPV4,\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_nvgre_eth_ipv4_udp,\t\tICE_INSET_IPV4_DST,\t\t\tICE_SW_INSET_DIST_NVGRE_IPV4_UDP,\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_nvgre_eth_ipv4_tcp,\t\tICE_INSET_IPV4_DST,\t\t\tICE_SW_INSET_DIST_NVGRE_IPV4_TCP,\tICE_INSET_NONE},\n+\t{pattern_eth_pppoes,\t\t\t\tICE_SW_INSET_MAC_PPPOE,\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_vlan_pppoes,\t\t\tICE_SW_INSET_MAC_PPPOE,\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_pppoes_proto,\t\t\tICE_SW_INSET_MAC_PPPOE_PROTO,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_vlan_pppoes_proto,\t\t\tICE_SW_INSET_MAC_PPPOE_PROTO,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_pppoes_ipv4,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV4,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_pppoes_ipv4_tcp,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV4_TCP,\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_pppoes_ipv4_udp,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV4_UDP,\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_pppoes_ipv6,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV6,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_pppoes_ipv6_tcp,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV6_TCP,\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_pppoes_ipv6_udp,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV6_UDP,\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_vlan_pppoes_ipv4,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV4,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_vlan_pppoes_ipv4_tcp,\t\tICE_SW_INSET_MAC_PPPOE_IPV4_TCP,\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_vlan_pppoes_ipv4_udp,\t\tICE_SW_INSET_MAC_PPPOE_IPV4_UDP,\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_vlan_pppoes_ipv6,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV6,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_vlan_pppoes_ipv6_tcp,\t\tICE_SW_INSET_MAC_PPPOE_IPV6_TCP,\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_vlan_pppoes_ipv6_udp,\t\tICE_SW_INSET_MAC_PPPOE_IPV6_UDP,\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_esp,\t\t\t\tICE_SW_INSET_MAC_IPV4_ESP,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_udp_esp,\t\t\tICE_SW_INSET_MAC_IPV4_ESP,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_esp,\t\t\t\tICE_SW_INSET_MAC_IPV6_ESP,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_udp_esp,\t\t\tICE_SW_INSET_MAC_IPV6_ESP,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_ah,\t\t\t\tICE_SW_INSET_MAC_IPV4_AH,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_ah,\t\t\t\tICE_SW_INSET_MAC_IPV6_AH,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_udp_ah,\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_l2tp,\t\t\t\tICE_SW_INSET_MAC_IPV4_L2TP,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_l2tp,\t\t\t\tICE_SW_INSET_MAC_IPV6_L2TP,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_pfcp,\t\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_pfcp,\t\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_qinq_ipv4,\t\t\t\tICE_SW_INSET_MAC_QINQ_IPV4,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_qinq_ipv6,\t\t\t\tICE_SW_INSET_MAC_QINQ_IPV6,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_qinq_pppoes,\t\t\tICE_SW_INSET_MAC_PPPOE,\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_qinq_pppoes_proto,\t\t\tICE_SW_INSET_MAC_PPPOE_PROTO,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_qinq_pppoes_ipv4,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV4,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_qinq_pppoes_ipv6,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV6,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu,\t\t\t\tICE_SW_INSET_MAC_IPV4_GTPU,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu,\t\t\t\tICE_SW_INSET_MAC_IPV6_GTPU,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_ipv4,\t\t\tICE_SW_INSET_MAC_GTPU_OUTER,\t\tICE_SW_INSET_GTPU_IPV4,\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_eh_ipv4,\t\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV4,\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_ipv4_udp,\t\tICE_SW_INSET_MAC_GTPU_OUTER,\t\tICE_SW_INSET_GTPU_IPV4_UDP,\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_eh_ipv4_udp,\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV4_UDP,\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_ipv4_tcp,\t\tICE_SW_INSET_MAC_GTPU_OUTER,\t\tICE_SW_INSET_GTPU_IPV4_TCP,\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_eh_ipv4_tcp,\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV4_TCP,\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_ipv6,\t\t\tICE_SW_INSET_MAC_GTPU_OUTER,\t\tICE_SW_INSET_GTPU_IPV6,\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_eh_ipv6,\t\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV6,\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_ipv6_udp,\t\tICE_SW_INSET_MAC_GTPU_OUTER,\t\tICE_SW_INSET_GTPU_IPV6_UDP,\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_eh_ipv6_udp,\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV6_UDP,\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_ipv6_tcp,\t\tICE_SW_INSET_MAC_GTPU_OUTER,\t\tICE_SW_INSET_GTPU_IPV6_TCP,\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_eh_ipv6_tcp,\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV6_TCP,\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_ipv4,\t\t\tICE_SW_INSET_MAC_GTPU_OUTER,\t\tICE_SW_INSET_GTPU_IPV4,\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_eh_ipv4,\t\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV4,\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_ipv4_udp,\t\tICE_SW_INSET_MAC_GTPU_OUTER,\t\tICE_SW_INSET_GTPU_IPV4_UDP,\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_eh_ipv4_udp,\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV4_UDP,\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_ipv4_tcp,\t\tICE_SW_INSET_MAC_GTPU_OUTER,\t\tICE_SW_INSET_GTPU_IPV4_TCP,\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_eh_ipv4_tcp,\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV4_TCP,\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_ipv6,\t\t\tICE_SW_INSET_MAC_GTPU_OUTER,\t\tICE_SW_INSET_GTPU_IPV6,\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_eh_ipv6,\t\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV6,\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_ipv6_udp,\t\tICE_SW_INSET_MAC_GTPU_OUTER,\t\tICE_SW_INSET_GTPU_IPV6_UDP,\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_eh_ipv6_udp,\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV6_UDP,\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_ipv6_tcp,\t\tICE_SW_INSET_MAC_GTPU_OUTER,\t\tICE_SW_INSET_GTPU_IPV6_TCP,\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_eh_ipv6_tcp,\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV6_TCP,\t\tICE_INSET_NONE},\n };\n \n static struct\n ice_pattern_match_item ice_switch_pattern_perm_list[] = {\n-\t{pattern_ethertype,\t\t\t\tICE_SW_INSET_ETHER,\t\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_ethertype_vlan,\t\t\tICE_SW_INSET_MAC_VLAN,\t\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_ethertype_qinq,\t\t\tICE_SW_INSET_MAC_QINQ,\t\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_arp,\t\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4,\t\t\t\tICE_SW_INSET_MAC_IPV4,\t\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_udp,\t\t\t\tICE_SW_INSET_MAC_IPV4_UDP,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_tcp,\t\t\t\tICE_SW_INSET_MAC_IPV4_TCP,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6,\t\t\t\tICE_SW_INSET_MAC_IPV6,\t\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6_udp,\t\t\t\tICE_SW_INSET_MAC_IPV6_UDP,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6_tcp,\t\t\t\tICE_SW_INSET_MAC_IPV6_TCP,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_udp_vxlan_eth_ipv4,\t\tICE_SW_INSET_PERM_TUNNEL_IPV4,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_udp_vxlan_eth_ipv4_udp,\tICE_SW_INSET_PERM_TUNNEL_IPV4_UDP,\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_udp_vxlan_eth_ipv4_tcp,\tICE_SW_INSET_PERM_TUNNEL_IPV4_TCP,\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_nvgre_eth_ipv4,\t\tICE_SW_INSET_PERM_TUNNEL_IPV4,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_nvgre_eth_ipv4_udp,\t\tICE_SW_INSET_PERM_TUNNEL_IPV4_UDP,\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_nvgre_eth_ipv4_tcp,\t\tICE_SW_INSET_PERM_TUNNEL_IPV4_TCP,\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_pppoes,\t\t\t\tICE_SW_INSET_MAC_PPPOE,\t\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_vlan_pppoes,\t\t\tICE_SW_INSET_MAC_PPPOE,\t\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_pppoes_proto,\t\t\tICE_SW_INSET_MAC_PPPOE_PROTO,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_vlan_pppoes_proto,\t\t\tICE_SW_INSET_MAC_PPPOE_PROTO,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_pppoes_ipv4,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV4,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_pppoes_ipv4_tcp,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV4_TCP,\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_pppoes_ipv4_udp,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV4_UDP,\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_pppoes_ipv6,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV6,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_pppoes_ipv6_tcp,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV6_TCP,\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_pppoes_ipv6_udp,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV6_UDP,\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_vlan_pppoes_ipv4,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV4,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_vlan_pppoes_ipv4_tcp,\t\tICE_SW_INSET_MAC_PPPOE_IPV4_TCP,\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_vlan_pppoes_ipv4_udp,\t\tICE_SW_INSET_MAC_PPPOE_IPV4_UDP,\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_vlan_pppoes_ipv6,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV6,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_vlan_pppoes_ipv6_tcp,\t\tICE_SW_INSET_MAC_PPPOE_IPV6_TCP,\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_vlan_pppoes_ipv6_udp,\t\tICE_SW_INSET_MAC_PPPOE_IPV6_UDP,\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_esp,\t\t\t\tICE_SW_INSET_MAC_IPV4_ESP,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_udp_esp,\t\t\tICE_SW_INSET_MAC_IPV4_ESP,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6_esp,\t\t\t\tICE_SW_INSET_MAC_IPV6_ESP,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6_udp_esp,\t\t\tICE_SW_INSET_MAC_IPV6_ESP,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_ah,\t\t\t\tICE_SW_INSET_MAC_IPV4_AH,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6_ah,\t\t\t\tICE_SW_INSET_MAC_IPV6_AH,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6_udp_ah,\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_l2tp,\t\t\t\tICE_SW_INSET_MAC_IPV4_L2TP,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6_l2tp,\t\t\t\tICE_SW_INSET_MAC_IPV6_L2TP,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_pfcp,\t\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv6_pfcp,\t\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_qinq_ipv4,\t\t\t\tICE_SW_INSET_MAC_QINQ_IPV4,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_qinq_ipv6,\t\t\t\tICE_SW_INSET_MAC_QINQ_IPV6,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_qinq_pppoes,\t\t\tICE_SW_INSET_MAC_PPPOE,\t\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_qinq_pppoes_proto,\t\t\tICE_SW_INSET_MAC_PPPOE_PROTO,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_qinq_pppoes_ipv4,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV4,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_qinq_pppoes_ipv6,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV6,\t\tICE_INSET_NONE,\tICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu,\t\t\t\tICE_SW_INSET_MAC_IPV4_GTPU,\t\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu,\t\t\t\tICE_SW_INSET_MAC_IPV6_GTPU,\t\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu_ipv4,\t\t\tICE_SW_INSET_MAC_IPV4_GTPU_IPV4,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu_eh_ipv4,\t\t\tICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV4,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu_ipv4_udp,\t\tICE_SW_INSET_MAC_IPV4_GTPU_IPV4_UDP,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu_eh_ipv4_udp,\t\tICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV4_UDP,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu_ipv4_tcp,\t\tICE_SW_INSET_MAC_IPV4_GTPU_IPV4_TCP,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu_eh_ipv4_tcp,\t\tICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV4_TCP,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu_ipv6,\t\t\tICE_SW_INSET_MAC_IPV4_GTPU_IPV6,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu_eh_ipv6,\t\t\tICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV6,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu_ipv6_udp,\t\tICE_SW_INSET_MAC_IPV4_GTPU_IPV6_UDP,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu_eh_ipv6_udp,\t\tICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV6_UDP,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu_ipv6_tcp,\t\tICE_SW_INSET_MAC_IPV4_GTPU_IPV6_TCP,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv4_gtpu_eh_ipv6_tcp,\t\tICE_SW_INSET_MAC_IPV4_GTPU_EH_IPV6_TCP,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu_ipv4,\t\t\tICE_SW_INSET_MAC_IPV6_GTPU_IPV4,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu_eh_ipv4,\t\t\tICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV4,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu_ipv4_udp,\t\tICE_SW_INSET_MAC_IPV6_GTPU_IPV4_UDP,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu_eh_ipv4_udp,\t\tICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV4_UDP,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu_ipv4_tcp,\t\tICE_SW_INSET_MAC_IPV6_GTPU_IPV4_TCP,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu_eh_ipv4_tcp,\t\tICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV4_TCP,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu_ipv6,\t\t\tICE_SW_INSET_MAC_IPV6_GTPU_IPV6,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu_eh_ipv6,\t\t\tICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV6,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu_ipv6_udp,\t\tICE_SW_INSET_MAC_IPV6_GTPU_IPV6_UDP,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu_eh_ipv6_udp,\t\tICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV6_UDP,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu_ipv6_tcp,\t\tICE_SW_INSET_MAC_IPV6_GTPU_IPV6_UDP,\tICE_INSET_NONE, ICE_INSET_NONE},\n-\t{pattern_eth_ipv6_gtpu_eh_ipv6_tcp,\t\tICE_SW_INSET_MAC_IPV6_GTPU_EH_IPV6_TCP,\tICE_INSET_NONE, ICE_INSET_NONE},\n+\t{pattern_ethertype,\t\t\t\tICE_SW_INSET_ETHER,\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_ethertype_vlan,\t\t\tICE_SW_INSET_MAC_VLAN,\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_ethertype_qinq,\t\t\tICE_SW_INSET_MAC_QINQ,\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_arp,\t\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4,\t\t\t\tICE_SW_INSET_MAC_IPV4,\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_udp,\t\t\t\tICE_SW_INSET_MAC_IPV4_UDP,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_tcp,\t\t\t\tICE_SW_INSET_MAC_IPV4_TCP,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6,\t\t\t\tICE_SW_INSET_MAC_IPV6,\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_udp,\t\t\t\tICE_SW_INSET_MAC_IPV6_UDP,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_tcp,\t\t\t\tICE_SW_INSET_MAC_IPV6_TCP,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_udp_vxlan_eth_ipv4,\t\tICE_INSET_NONE,\t\t\t\tICE_SW_INSET_PERM_TUNNEL_IPV4,\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_udp_vxlan_eth_ipv4_udp,\tICE_INSET_NONE,\t\t\t\tICE_SW_INSET_PERM_TUNNEL_IPV4_UDP,\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_udp_vxlan_eth_ipv4_tcp,\tICE_INSET_NONE,\t\t\t\tICE_SW_INSET_PERM_TUNNEL_IPV4_TCP,\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_nvgre_eth_ipv4,\t\tICE_INSET_NONE,\t\t\t\tICE_SW_INSET_PERM_TUNNEL_IPV4,\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_nvgre_eth_ipv4_udp,\t\tICE_INSET_NONE,\t\t\t\tICE_SW_INSET_PERM_TUNNEL_IPV4_UDP,\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_nvgre_eth_ipv4_tcp,\t\tICE_INSET_NONE,\t\t\t\tICE_SW_INSET_PERM_TUNNEL_IPV4_TCP,\tICE_INSET_NONE},\n+\t{pattern_eth_pppoes,\t\t\t\tICE_SW_INSET_MAC_PPPOE,\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_vlan_pppoes,\t\t\tICE_SW_INSET_MAC_PPPOE,\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_pppoes_proto,\t\t\tICE_SW_INSET_MAC_PPPOE_PROTO,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_vlan_pppoes_proto,\t\t\tICE_SW_INSET_MAC_PPPOE_PROTO,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_pppoes_ipv4,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV4,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_pppoes_ipv4_tcp,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV4_TCP,\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_pppoes_ipv4_udp,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV4_UDP,\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_pppoes_ipv6,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV6,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_pppoes_ipv6_tcp,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV6_TCP,\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_pppoes_ipv6_udp,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV6_UDP,\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_vlan_pppoes_ipv4,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV4,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_vlan_pppoes_ipv4_tcp,\t\tICE_SW_INSET_MAC_PPPOE_IPV4_TCP,\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_vlan_pppoes_ipv4_udp,\t\tICE_SW_INSET_MAC_PPPOE_IPV4_UDP,\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_vlan_pppoes_ipv6,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV6,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_vlan_pppoes_ipv6_tcp,\t\tICE_SW_INSET_MAC_PPPOE_IPV6_TCP,\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_vlan_pppoes_ipv6_udp,\t\tICE_SW_INSET_MAC_PPPOE_IPV6_UDP,\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_esp,\t\t\t\tICE_SW_INSET_MAC_IPV4_ESP,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_udp_esp,\t\t\tICE_SW_INSET_MAC_IPV4_ESP,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_esp,\t\t\t\tICE_SW_INSET_MAC_IPV6_ESP,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_udp_esp,\t\t\tICE_SW_INSET_MAC_IPV6_ESP,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_ah,\t\t\t\tICE_SW_INSET_MAC_IPV4_AH,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_ah,\t\t\t\tICE_SW_INSET_MAC_IPV6_AH,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_udp_ah,\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_l2tp,\t\t\t\tICE_SW_INSET_MAC_IPV4_L2TP,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_l2tp,\t\t\t\tICE_SW_INSET_MAC_IPV6_L2TP,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_pfcp,\t\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_pfcp,\t\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_qinq_ipv4,\t\t\t\tICE_SW_INSET_MAC_QINQ_IPV4,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_qinq_ipv6,\t\t\t\tICE_SW_INSET_MAC_QINQ_IPV6,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_qinq_pppoes,\t\t\tICE_SW_INSET_MAC_PPPOE,\t\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_qinq_pppoes_proto,\t\t\tICE_SW_INSET_MAC_PPPOE_PROTO,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_qinq_pppoes_ipv4,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV4,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_qinq_pppoes_ipv6,\t\t\tICE_SW_INSET_MAC_PPPOE_IPV6,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu,\t\t\t\tICE_SW_INSET_MAC_IPV4_GTPU,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu,\t\t\t\tICE_SW_INSET_MAC_IPV6_GTPU,\t\tICE_INSET_NONE,\t\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_ipv4,\t\t\tICE_SW_INSET_MAC_GTPU_OUTER,\t\tICE_SW_INSET_GTPU_IPV4,\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_eh_ipv4,\t\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV4,\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_ipv4_udp,\t\tICE_SW_INSET_MAC_GTPU_OUTER,\t\tICE_SW_INSET_GTPU_IPV4_UDP,\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_eh_ipv4_udp,\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV4_UDP,\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_ipv4_tcp,\t\tICE_SW_INSET_MAC_GTPU_OUTER,\t\tICE_SW_INSET_GTPU_IPV4_TCP,\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_eh_ipv4_tcp,\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV4_TCP,\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_ipv6,\t\t\tICE_SW_INSET_MAC_GTPU_OUTER,\t\tICE_SW_INSET_GTPU_IPV6,\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_eh_ipv6,\t\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV6,\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_ipv6_udp,\t\tICE_SW_INSET_MAC_GTPU_OUTER,\t\tICE_SW_INSET_GTPU_IPV6_UDP,\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_eh_ipv6_udp,\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV6_UDP,\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_ipv6_tcp,\t\tICE_SW_INSET_MAC_GTPU_OUTER,\t\tICE_SW_INSET_GTPU_IPV6_TCP,\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv4_gtpu_eh_ipv6_tcp,\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV6_TCP,\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_ipv4,\t\t\tICE_SW_INSET_MAC_GTPU_OUTER,\t\tICE_SW_INSET_GTPU_IPV4,\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_eh_ipv4,\t\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV4,\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_ipv4_udp,\t\tICE_SW_INSET_MAC_GTPU_OUTER,\t\tICE_SW_INSET_GTPU_IPV4_UDP,\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_eh_ipv4_udp,\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV4_UDP,\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_ipv4_tcp,\t\tICE_SW_INSET_MAC_GTPU_OUTER,\t\tICE_SW_INSET_GTPU_IPV4_TCP,\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_eh_ipv4_tcp,\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV4_TCP,\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_ipv6,\t\t\tICE_SW_INSET_MAC_GTPU_OUTER,\t\tICE_SW_INSET_GTPU_IPV6,\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_eh_ipv6,\t\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV6,\t\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_ipv6_udp,\t\tICE_SW_INSET_MAC_GTPU_OUTER,\t\tICE_SW_INSET_GTPU_IPV6_UDP,\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_eh_ipv6_udp,\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV6_UDP,\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_ipv6_tcp,\t\tICE_SW_INSET_MAC_GTPU_OUTER,\t\tICE_SW_INSET_GTPU_IPV6_TCP,\t\tICE_INSET_NONE},\n+\t{pattern_eth_ipv6_gtpu_eh_ipv6_tcp,\t\tICE_SW_INSET_MAC_GTPU_EH_OUTER,\t\tICE_SW_INSET_GTPU_IPV6_TCP,\t\tICE_INSET_NONE},\n };\n \n static int\n@@ -477,12 +428,13 @@ ice_switch_filter_rule_free(struct rte_flow *flow)\n \trte_free(flow->rule);\n }\n \n-static uint64_t\n-ice_switch_inset_get(const struct rte_flow_item pattern[],\n+static bool\n+ice_switch_parse_pattern(const struct rte_flow_item pattern[],\n \t\tstruct rte_flow_error *error,\n \t\tstruct ice_adv_lkup_elem *list,\n \t\tuint16_t *lkups_num,\n-\t\tenum ice_sw_tunnel_type *tun_type)\n+\t\tenum ice_sw_tunnel_type *tun_type,\n+\t\tconst struct ice_pattern_match_item pattern_match_item)\n {\n \tconst struct rte_flow_item *item = pattern;\n \tenum rte_flow_item_type item_type;\n@@ -504,7 +456,9 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \tconst struct rte_flow_item_pfcp *pfcp_spec, *pfcp_mask;\n \tconst struct rte_flow_item_gtp *gtp_spec, *gtp_mask;\n \tconst struct rte_flow_item_gtp_psc *gtp_psc_spec, *gtp_psc_mask;\n-\tuint64_t input_set = ICE_INSET_NONE;\n+\tuint64_t outer_input_set = ICE_INSET_NONE;\n+\tuint64_t inner_input_set = ICE_INSET_NONE;\n+\tuint64_t *input = NULL;\n \tuint16_t input_set_byte = 0;\n \tbool pppoe_elem_valid = 0;\n \tbool pppoe_patt_valid = 0;\n@@ -539,7 +493,7 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\t\t\tRTE_FLOW_ERROR_TYPE_ITEM,\n \t\t\t\t\titem,\n \t\t\t\t\t\"Not support range\");\n-\t\t\treturn 0;\n+\t\t\treturn false;\n \t\t}\n \t\titem_type = item->type;\n \n@@ -550,30 +504,24 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\tif (eth_spec && eth_mask) {\n \t\t\t\tconst uint8_t *a = eth_mask->src.addr_bytes;\n \t\t\t\tconst uint8_t *b = eth_mask->dst.addr_bytes;\n+\t\t\t\tif (tunnel_valid)\n+\t\t\t\t\tinput = &inner_input_set;\n+\t\t\t\telse\n+\t\t\t\t\tinput = &outer_input_set;\n \t\t\t\tfor (j = 0; j < RTE_ETHER_ADDR_LEN; j++) {\n-\t\t\t\t\tif (a[j] && tunnel_valid) {\n-\t\t\t\t\t\tinput_set |=\n-\t\t\t\t\t\t\tICE_INSET_TUN_SMAC;\n-\t\t\t\t\t\tbreak;\n-\t\t\t\t\t} else if (a[j]) {\n-\t\t\t\t\t\tinput_set |=\n-\t\t\t\t\t\t\tICE_INSET_SMAC;\n+\t\t\t\t\tif (a[j]) {\n+\t\t\t\t\t\t*input |= ICE_INSET_SMAC;\n \t\t\t\t\t\tbreak;\n \t\t\t\t\t}\n \t\t\t\t}\n \t\t\t\tfor (j = 0; j < RTE_ETHER_ADDR_LEN; j++) {\n-\t\t\t\t\tif (b[j] && tunnel_valid) {\n-\t\t\t\t\t\tinput_set |=\n-\t\t\t\t\t\t\tICE_INSET_TUN_DMAC;\n-\t\t\t\t\t\tbreak;\n-\t\t\t\t\t} else if (b[j]) {\n-\t\t\t\t\t\tinput_set |=\n-\t\t\t\t\t\t\tICE_INSET_DMAC;\n+\t\t\t\t\tif (b[j]) {\n+\t\t\t\t\t\t*input |= ICE_INSET_DMAC;\n \t\t\t\t\t\tbreak;\n \t\t\t\t\t}\n \t\t\t\t}\n \t\t\t\tif (eth_mask->type)\n-\t\t\t\t\tinput_set |= ICE_INSET_ETHERTYPE;\n+\t\t\t\t\t*input |= ICE_INSET_ETHERTYPE;\n \t\t\t\tlist[t].type = (tunnel_valid  == 0) ?\n \t\t\t\t\tICE_MAC_OFOS : ICE_MAC_IL;\n \t\t\t\tstruct ice_ether_hdr *h;\n@@ -616,10 +564,13 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\tcase RTE_FLOW_ITEM_TYPE_IPV4:\n \t\t\tipv4_spec = item->spec;\n \t\t\tipv4_mask = item->mask;\n-\t\t\tif (tunnel_valid)\n+\t\t\tif (tunnel_valid) {\n \t\t\t\tinner_ipv4_valid = 1;\n-\t\t\telse\n+\t\t\t\tinput = &inner_input_set;\n+\t\t\t} else {\n \t\t\t\tipv4_valid = 1;\n+\t\t\t\tinput = &outer_input_set;\n+\t\t\t}\n \n \t\t\tif (ipv4_spec && ipv4_mask) {\n \t\t\t\t/* Check IPv4 mask and update input set */\n@@ -631,39 +582,20 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\t\t\t\t   RTE_FLOW_ERROR_TYPE_ITEM,\n \t\t\t\t\t\t   item,\n \t\t\t\t\t\t   \"Invalid IPv4 mask.\");\n-\t\t\t\t\treturn 0;\n+\t\t\t\t\treturn false;\n \t\t\t\t}\n \n-\t\t\t\tif (tunnel_valid) {\n-\t\t\t\t\tif (ipv4_mask->hdr.type_of_service)\n-\t\t\t\t\t\tinput_set |=\n-\t\t\t\t\t\t\tICE_INSET_TUN_IPV4_TOS;\n-\t\t\t\t\tif (ipv4_mask->hdr.src_addr)\n-\t\t\t\t\t\tinput_set |=\n-\t\t\t\t\t\t\tICE_INSET_TUN_IPV4_SRC;\n-\t\t\t\t\tif (ipv4_mask->hdr.dst_addr)\n-\t\t\t\t\t\tinput_set |=\n-\t\t\t\t\t\t\tICE_INSET_TUN_IPV4_DST;\n-\t\t\t\t\tif (ipv4_mask->hdr.time_to_live)\n-\t\t\t\t\t\tinput_set |=\n-\t\t\t\t\t\t\tICE_INSET_TUN_IPV4_TTL;\n-\t\t\t\t\tif (ipv4_mask->hdr.next_proto_id)\n-\t\t\t\t\t\tinput_set |=\n-\t\t\t\t\t\tICE_INSET_TUN_IPV4_PROTO;\n-\t\t\t\t} else {\n-\t\t\t\t\tif (ipv4_mask->hdr.src_addr)\n-\t\t\t\t\t\tinput_set |= ICE_INSET_IPV4_SRC;\n-\t\t\t\t\tif (ipv4_mask->hdr.dst_addr)\n-\t\t\t\t\t\tinput_set |= ICE_INSET_IPV4_DST;\n-\t\t\t\t\tif (ipv4_mask->hdr.time_to_live)\n-\t\t\t\t\t\tinput_set |= ICE_INSET_IPV4_TTL;\n-\t\t\t\t\tif (ipv4_mask->hdr.next_proto_id)\n-\t\t\t\t\t\tinput_set |=\n-\t\t\t\t\t\tICE_INSET_IPV4_PROTO;\n-\t\t\t\t\tif (ipv4_mask->hdr.type_of_service)\n-\t\t\t\t\t\tinput_set |=\n-\t\t\t\t\t\t\tICE_INSET_IPV4_TOS;\n-\t\t\t\t}\n+\t\t\t\tif (ipv4_mask->hdr.src_addr)\n+\t\t\t\t\t*input |= ICE_INSET_IPV4_SRC;\n+\t\t\t\tif (ipv4_mask->hdr.dst_addr)\n+\t\t\t\t\t*input |= ICE_INSET_IPV4_DST;\n+\t\t\t\tif (ipv4_mask->hdr.time_to_live)\n+\t\t\t\t\t*input |= ICE_INSET_IPV4_TTL;\n+\t\t\t\tif (ipv4_mask->hdr.next_proto_id)\n+\t\t\t\t\t*input |= ICE_INSET_IPV4_PROTO;\n+\t\t\t\tif (ipv4_mask->hdr.type_of_service)\n+\t\t\t\t\t*input |= ICE_INSET_IPV4_TOS;\n+\n \t\t\t\tlist[t].type = (tunnel_valid  == 0) ?\n \t\t\t\t\tICE_IPV4_OFOS : ICE_IPV4_IL;\n \t\t\t\tif (ipv4_mask->hdr.src_addr) {\n@@ -712,65 +644,42 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\tcase RTE_FLOW_ITEM_TYPE_IPV6:\n \t\t\tipv6_spec = item->spec;\n \t\t\tipv6_mask = item->mask;\n-\t\t\tif (tunnel_valid)\n+\t\t\tif (tunnel_valid) {\n \t\t\t\tinner_ipv6_valid = 1;\n-\t\t\telse\n+\t\t\t\tinput = &inner_input_set;\n+\t\t\t} else {\n \t\t\t\tipv6_valid = 1;\n+\t\t\t\tinput = &outer_input_set;\n+\t\t\t}\n+\n \t\t\tif (ipv6_spec && ipv6_mask) {\n \t\t\t\tif (ipv6_mask->hdr.payload_len) {\n \t\t\t\t\trte_flow_error_set(error, EINVAL,\n \t\t\t\t\t   RTE_FLOW_ERROR_TYPE_ITEM,\n \t\t\t\t\t   item,\n \t\t\t\t\t   \"Invalid IPv6 mask\");\n-\t\t\t\t\treturn 0;\n+\t\t\t\t\treturn false;\n \t\t\t\t}\n \n \t\t\t\tfor (j = 0; j < ICE_IPV6_ADDR_LENGTH; j++) {\n-\t\t\t\t\tif (ipv6_mask->hdr.src_addr[j] &&\n-\t\t\t\t\t\ttunnel_valid) {\n-\t\t\t\t\t\tinput_set |=\n-\t\t\t\t\t\tICE_INSET_TUN_IPV6_SRC;\n-\t\t\t\t\t\tbreak;\n-\t\t\t\t\t} else if (ipv6_mask->hdr.src_addr[j]) {\n-\t\t\t\t\t\tinput_set |= ICE_INSET_IPV6_SRC;\n+\t\t\t\t\tif (ipv6_mask->hdr.src_addr[j]) {\n+\t\t\t\t\t\t*input |= ICE_INSET_IPV6_SRC;\n \t\t\t\t\t\tbreak;\n \t\t\t\t\t}\n \t\t\t\t}\n \t\t\t\tfor (j = 0; j < ICE_IPV6_ADDR_LENGTH; j++) {\n-\t\t\t\t\tif (ipv6_mask->hdr.dst_addr[j] &&\n-\t\t\t\t\t\ttunnel_valid) {\n-\t\t\t\t\t\tinput_set |=\n-\t\t\t\t\t\tICE_INSET_TUN_IPV6_DST;\n-\t\t\t\t\t\tbreak;\n-\t\t\t\t\t} else if (ipv6_mask->hdr.dst_addr[j]) {\n-\t\t\t\t\t\tinput_set |= ICE_INSET_IPV6_DST;\n+\t\t\t\t\tif (ipv6_mask->hdr.dst_addr[j]) {\n+\t\t\t\t\t\t*input |= ICE_INSET_IPV6_DST;\n \t\t\t\t\t\tbreak;\n \t\t\t\t\t}\n \t\t\t\t}\n-\t\t\t\tif (ipv6_mask->hdr.proto &&\n-\t\t\t\t\ttunnel_valid)\n-\t\t\t\t\tinput_set |=\n-\t\t\t\t\t\tICE_INSET_TUN_IPV6_NEXT_HDR;\n-\t\t\t\telse if (ipv6_mask->hdr.proto)\n-\t\t\t\t\tinput_set |=\n-\t\t\t\t\t\tICE_INSET_IPV6_NEXT_HDR;\n-\t\t\t\tif (ipv6_mask->hdr.hop_limits &&\n-\t\t\t\t\ttunnel_valid)\n-\t\t\t\t\tinput_set |=\n-\t\t\t\t\t\tICE_INSET_TUN_IPV6_HOP_LIMIT;\n-\t\t\t\telse if (ipv6_mask->hdr.hop_limits)\n-\t\t\t\t\tinput_set |=\n-\t\t\t\t\t\tICE_INSET_IPV6_HOP_LIMIT;\n-\t\t\t\tif ((ipv6_mask->hdr.vtc_flow &\n-\t\t\t\t\t\trte_cpu_to_be_32\n-\t\t\t\t\t\t(RTE_IPV6_HDR_TC_MASK)) &&\n-\t\t\t\t\ttunnel_valid)\n-\t\t\t\t\tinput_set |=\n-\t\t\t\t\t\t\tICE_INSET_TUN_IPV6_TC;\n-\t\t\t\telse if (ipv6_mask->hdr.vtc_flow &\n-\t\t\t\t\t\trte_cpu_to_be_32\n-\t\t\t\t\t\t(RTE_IPV6_HDR_TC_MASK))\n-\t\t\t\t\tinput_set |= ICE_INSET_IPV6_TC;\n+\t\t\t\tif (ipv6_mask->hdr.proto)\n+\t\t\t\t\t*input |= ICE_INSET_IPV6_NEXT_HDR;\n+\t\t\t\tif (ipv6_mask->hdr.hop_limits)\n+\t\t\t\t\t*input |= ICE_INSET_IPV6_HOP_LIMIT;\n+\t\t\t\tif (ipv6_mask->hdr.vtc_flow &\n+\t\t\t\t    rte_cpu_to_be_32(RTE_IPV6_HDR_TC_MASK))\n+\t\t\t\t\t*input |= ICE_INSET_IPV6_TC;\n \n \t\t\t\tlist[t].type = (tunnel_valid  == 0) ?\n \t\t\t\t\tICE_IPV6_OFOS : ICE_IPV6_IL;\n@@ -833,10 +742,14 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\tcase RTE_FLOW_ITEM_TYPE_UDP:\n \t\t\tudp_spec = item->spec;\n \t\t\tudp_mask = item->mask;\n-\t\t\tif (tunnel_valid)\n+\t\t\tif (tunnel_valid) {\n \t\t\t\tinner_udp_valid = 1;\n-\t\t\telse\n+\t\t\t\tinput = &inner_input_set;\n+\t\t\t} else {\n \t\t\t\tudp_valid = 1;\n+\t\t\t\tinput = &outer_input_set;\n+\t\t\t}\n+\n \t\t\tif (udp_spec && udp_mask) {\n \t\t\t\t/* Check UDP mask and update input set*/\n \t\t\t\tif (udp_mask->hdr.dgram_len ||\n@@ -845,24 +758,14 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\t\t\t\t   RTE_FLOW_ERROR_TYPE_ITEM,\n \t\t\t\t\t\t   item,\n \t\t\t\t\t\t   \"Invalid UDP mask\");\n-\t\t\t\t\treturn 0;\n+\t\t\t\t\treturn false;\n \t\t\t\t}\n \n-\t\t\t\tif (tunnel_valid) {\n-\t\t\t\t\tif (udp_mask->hdr.src_port)\n-\t\t\t\t\t\tinput_set |=\n-\t\t\t\t\t\tICE_INSET_TUN_UDP_SRC_PORT;\n-\t\t\t\t\tif (udp_mask->hdr.dst_port)\n-\t\t\t\t\t\tinput_set |=\n-\t\t\t\t\t\tICE_INSET_TUN_UDP_DST_PORT;\n-\t\t\t\t} else {\n-\t\t\t\t\tif (udp_mask->hdr.src_port)\n-\t\t\t\t\t\tinput_set |=\n-\t\t\t\t\t\tICE_INSET_UDP_SRC_PORT;\n-\t\t\t\t\tif (udp_mask->hdr.dst_port)\n-\t\t\t\t\t\tinput_set |=\n-\t\t\t\t\t\tICE_INSET_UDP_DST_PORT;\n-\t\t\t\t}\n+\t\t\t\tif (udp_mask->hdr.src_port)\n+\t\t\t\t\t*input |= ICE_INSET_UDP_SRC_PORT;\n+\t\t\t\tif (udp_mask->hdr.dst_port)\n+\t\t\t\t\t*input |= ICE_INSET_UDP_DST_PORT;\n+\n \t\t\t\tif (*tun_type == ICE_SW_TUN_VXLAN &&\n \t\t\t\t\t\ttunnel_valid == 0)\n \t\t\t\t\tlist[t].type = ICE_UDP_OF;\n@@ -889,10 +792,14 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\tcase RTE_FLOW_ITEM_TYPE_TCP:\n \t\t\ttcp_spec = item->spec;\n \t\t\ttcp_mask = item->mask;\n-\t\t\tif (tunnel_valid)\n+\t\t\tif (tunnel_valid) {\n \t\t\t\tinner_tcp_valid = 1;\n-\t\t\telse\n+\t\t\t\tinput = &inner_input_set;\n+\t\t\t} else {\n \t\t\t\ttcp_valid = 1;\n+\t\t\t\tinput = &outer_input_set;\n+\t\t\t}\n+\n \t\t\tif (tcp_spec && tcp_mask) {\n \t\t\t\t/* Check TCP mask and update input set */\n \t\t\t\tif (tcp_mask->hdr.sent_seq ||\n@@ -906,24 +813,13 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\t\t\t   RTE_FLOW_ERROR_TYPE_ITEM,\n \t\t\t\t\t   item,\n \t\t\t\t\t   \"Invalid TCP mask\");\n-\t\t\t\t\treturn 0;\n+\t\t\t\t\treturn false;\n \t\t\t\t}\n \n-\t\t\t\tif (tunnel_valid) {\n-\t\t\t\t\tif (tcp_mask->hdr.src_port)\n-\t\t\t\t\t\tinput_set |=\n-\t\t\t\t\t\tICE_INSET_TUN_TCP_SRC_PORT;\n-\t\t\t\t\tif (tcp_mask->hdr.dst_port)\n-\t\t\t\t\t\tinput_set |=\n-\t\t\t\t\t\tICE_INSET_TUN_TCP_DST_PORT;\n-\t\t\t\t} else {\n-\t\t\t\t\tif (tcp_mask->hdr.src_port)\n-\t\t\t\t\t\tinput_set |=\n-\t\t\t\t\t\tICE_INSET_TCP_SRC_PORT;\n-\t\t\t\t\tif (tcp_mask->hdr.dst_port)\n-\t\t\t\t\t\tinput_set |=\n-\t\t\t\t\t\tICE_INSET_TCP_DST_PORT;\n-\t\t\t\t}\n+\t\t\t\tif (tcp_mask->hdr.src_port)\n+\t\t\t\t\t*input |= ICE_INSET_TCP_SRC_PORT;\n+\t\t\t\tif (tcp_mask->hdr.dst_port)\n+\t\t\t\t\t*input |= ICE_INSET_TCP_DST_PORT;\n \t\t\t\tlist[t].type = ICE_TCP_IL;\n \t\t\t\tif (tcp_mask->hdr.src_port) {\n \t\t\t\t\tlist[t].h_u.l4_hdr.src_port =\n@@ -953,24 +849,18 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\t\t\t   RTE_FLOW_ERROR_TYPE_ITEM,\n \t\t\t\t\t   item,\n \t\t\t\t\t   \"Invalid SCTP mask\");\n-\t\t\t\t\treturn 0;\n+\t\t\t\t\treturn false;\n \t\t\t\t}\n+\t\t\t\tif (tunnel_valid)\n+\t\t\t\t\tinput = &inner_input_set;\n+\t\t\t\telse\n+\t\t\t\t\tinput = &outer_input_set;\n+\n+\t\t\t\tif (sctp_mask->hdr.src_port)\n+\t\t\t\t\t*input |= ICE_INSET_SCTP_SRC_PORT;\n+\t\t\t\tif (sctp_mask->hdr.dst_port)\n+\t\t\t\t\t*input |= ICE_INSET_SCTP_DST_PORT;\n \n-\t\t\t\tif (tunnel_valid) {\n-\t\t\t\t\tif (sctp_mask->hdr.src_port)\n-\t\t\t\t\t\tinput_set |=\n-\t\t\t\t\t\tICE_INSET_TUN_SCTP_SRC_PORT;\n-\t\t\t\t\tif (sctp_mask->hdr.dst_port)\n-\t\t\t\t\t\tinput_set |=\n-\t\t\t\t\t\tICE_INSET_TUN_SCTP_DST_PORT;\n-\t\t\t\t} else {\n-\t\t\t\t\tif (sctp_mask->hdr.src_port)\n-\t\t\t\t\t\tinput_set |=\n-\t\t\t\t\t\tICE_INSET_SCTP_SRC_PORT;\n-\t\t\t\t\tif (sctp_mask->hdr.dst_port)\n-\t\t\t\t\t\tinput_set |=\n-\t\t\t\t\t\tICE_INSET_SCTP_DST_PORT;\n-\t\t\t\t}\n \t\t\t\tlist[t].type = ICE_SCTP_IL;\n \t\t\t\tif (sctp_mask->hdr.src_port) {\n \t\t\t\t\tlist[t].h_u.sctp_hdr.src_port =\n@@ -1003,10 +893,11 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\t\t\t   RTE_FLOW_ERROR_TYPE_ITEM,\n \t\t\t\t\t   item,\n \t\t\t\t\t   \"Invalid VXLAN item\");\n-\t\t\t\treturn 0;\n+\t\t\t\treturn false;\n \t\t\t}\n \t\t\tvxlan_valid = 1;\n \t\t\ttunnel_valid = 1;\n+\t\t\tinput = &inner_input_set;\n \t\t\tif (vxlan_spec && vxlan_mask) {\n \t\t\t\tlist[t].type = ICE_VXLAN;\n \t\t\t\tif (vxlan_mask->vni[0] ||\n@@ -1020,8 +911,7 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\t\t\t\t(vxlan_mask->vni[2] << 16) |\n \t\t\t\t\t\t(vxlan_mask->vni[1] << 8) |\n \t\t\t\t\t\tvxlan_mask->vni[0];\n-\t\t\t\t\tinput_set |=\n-\t\t\t\t\t\tICE_INSET_TUN_VXLAN_VNI;\n+\t\t\t\t\t*input |= ICE_INSET_TUN_VXLAN_VNI;\n \t\t\t\t\tinput_set_byte += 2;\n \t\t\t\t}\n \t\t\t\tt++;\n@@ -1041,10 +931,11 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\t\t\t   RTE_FLOW_ERROR_TYPE_ITEM,\n \t\t\t\t\t   item,\n \t\t\t\t\t   \"Invalid NVGRE item\");\n-\t\t\t\treturn 0;\n+\t\t\t\treturn false;\n \t\t\t}\n \t\t\tnvgre_valid = 1;\n \t\t\ttunnel_valid = 1;\n+\t\t\tinput = &inner_input_set;\n \t\t\tif (nvgre_spec && nvgre_mask) {\n \t\t\t\tlist[t].type = ICE_NVGRE;\n \t\t\t\tif (nvgre_mask->tni[0] ||\n@@ -1058,8 +949,7 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\t\t\t\t(nvgre_mask->tni[2] << 16) |\n \t\t\t\t\t\t(nvgre_mask->tni[1] << 8) |\n \t\t\t\t\t\tnvgre_mask->tni[0];\n-\t\t\t\t\tinput_set |=\n-\t\t\t\t\t\tICE_INSET_TUN_NVGRE_TNI;\n+\t\t\t\t\t*input |= ICE_INSET_TUN_NVGRE_TNI;\n \t\t\t\t\tinput_set_byte += 2;\n \t\t\t\t}\n \t\t\t\tt++;\n@@ -1079,7 +969,7 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\t\t\t   RTE_FLOW_ERROR_TYPE_ITEM,\n \t\t\t\t\t   item,\n \t\t\t\t\t   \"Invalid VLAN item\");\n-\t\t\t\treturn 0;\n+\t\t\t\treturn false;\n \t\t\t}\n \n \t\t\tif (qinq_valid) {\n@@ -1089,20 +979,22 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\t\t\tinner_vlan_valid = 1;\n \t\t\t}\n \n+\t\t\tinput = &outer_input_set;\n+\n \t\t\tif (vlan_spec && vlan_mask) {\n \t\t\t\tif (qinq_valid) {\n \t\t\t\t\tif (!inner_vlan_valid) {\n \t\t\t\t\t\tlist[t].type = ICE_VLAN_EX;\n-\t\t\t\t\t\tinput_set |=\n+\t\t\t\t\t\t*input |=\n \t\t\t\t\t\t\tICE_INSET_VLAN_OUTER;\n \t\t\t\t\t} else {\n \t\t\t\t\t\tlist[t].type = ICE_VLAN_IN;\n-\t\t\t\t\t\tinput_set |=\n+\t\t\t\t\t\t*input |=\n \t\t\t\t\t\t\tICE_INSET_VLAN_INNER;\n \t\t\t\t\t}\n \t\t\t\t} else {\n \t\t\t\t\tlist[t].type = ICE_VLAN_OFOS;\n-\t\t\t\t\tinput_set |= ICE_INSET_VLAN_INNER;\n+\t\t\t\t\t*input |= ICE_INSET_VLAN_INNER;\n \t\t\t\t}\n \n \t\t\t\tif (vlan_mask->tci) {\n@@ -1117,7 +1009,7 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\t\t\t\tRTE_FLOW_ERROR_TYPE_ITEM,\n \t\t\t\t\t\titem,\n \t\t\t\t\t\t\"Invalid VLAN input set.\");\n-\t\t\t\t\treturn 0;\n+\t\t\t\t\treturn false;\n \t\t\t\t}\n \t\t\t\tt++;\n \t\t\t}\n@@ -1137,9 +1029,10 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\t\t\tRTE_FLOW_ERROR_TYPE_ITEM,\n \t\t\t\t\titem,\n \t\t\t\t\t\"Invalid pppoe item\");\n-\t\t\t\treturn 0;\n+\t\t\t\treturn false;\n \t\t\t}\n \t\t\tpppoe_patt_valid = 1;\n+\t\t\tinput = &outer_input_set;\n \t\t\tif (pppoe_spec && pppoe_mask) {\n \t\t\t\t/* Check pppoe mask and update input set */\n \t\t\t\tif (pppoe_mask->length ||\n@@ -1149,7 +1042,7 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\t\t\t\tRTE_FLOW_ERROR_TYPE_ITEM,\n \t\t\t\t\t\titem,\n \t\t\t\t\t\t\"Invalid pppoe mask\");\n-\t\t\t\t\treturn 0;\n+\t\t\t\t\treturn false;\n \t\t\t\t}\n \t\t\t\tlist[t].type = ICE_PPPOE;\n \t\t\t\tif (pppoe_mask->session_id) {\n@@ -1157,7 +1050,7 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\t\t\t\tpppoe_spec->session_id;\n \t\t\t\t\tlist[t].m_u.pppoe_hdr.session_id =\n \t\t\t\t\t\tpppoe_mask->session_id;\n-\t\t\t\t\tinput_set |= ICE_INSET_PPPOE_SESSION;\n+\t\t\t\t\t*input |= ICE_INSET_PPPOE_SESSION;\n \t\t\t\t\tinput_set_byte += 2;\n \t\t\t\t}\n \t\t\t\tt++;\n@@ -1179,8 +1072,9 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\t\t\tRTE_FLOW_ERROR_TYPE_ITEM,\n \t\t\t\t\titem,\n \t\t\t\t\t\"Invalid pppoe proto item\");\n-\t\t\t\treturn 0;\n+\t\t\t\treturn false;\n \t\t\t}\n+\t\t\tinput = &outer_input_set;\n \t\t\tif (pppoe_proto_spec && pppoe_proto_mask) {\n \t\t\t\tif (pppoe_elem_valid)\n \t\t\t\t\tt--;\n@@ -1190,7 +1084,7 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\t\t\t\tpppoe_proto_spec->proto_id;\n \t\t\t\t\tlist[t].m_u.pppoe_hdr.ppp_prot_id =\n \t\t\t\t\t\tpppoe_proto_mask->proto_id;\n-\t\t\t\t\tinput_set |= ICE_INSET_PPPOE_PROTO;\n+\t\t\t\t\t*input |= ICE_INSET_PPPOE_PROTO;\n \t\t\t\t\tinput_set_byte += 2;\n \t\t\t\t\tpppoe_prot_valid = 1;\n \t\t\t\t}\n@@ -1217,7 +1111,7 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\t\t\t   RTE_FLOW_ERROR_TYPE_ITEM,\n \t\t\t\t\t   item,\n \t\t\t\t\t   \"Invalid esp item\");\n-\t\t\t\treturn 0;\n+\t\t\t\treturn false;\n \t\t\t}\n \t\t\t/* Check esp mask and update input set */\n \t\t\tif (esp_mask && esp_mask->hdr.seq) {\n@@ -1225,10 +1119,10 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\t\t\t\tRTE_FLOW_ERROR_TYPE_ITEM,\n \t\t\t\t\t\titem,\n \t\t\t\t\t\t\"Invalid esp mask\");\n-\t\t\t\treturn 0;\n+\t\t\t\treturn false;\n \t\t\t}\n-\n-\t\t\tif (!esp_spec && !esp_mask && !input_set) {\n+\t\t\tinput = &outer_input_set;\n+\t\t\tif (!esp_spec && !esp_mask && !(*input)) {\n \t\t\t\tprofile_rule = 1;\n \t\t\t\tif (ipv6_valid && udp_valid)\n \t\t\t\t\t*tun_type =\n@@ -1236,7 +1130,7 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\t\telse if (ipv6_valid)\n \t\t\t\t\t*tun_type = ICE_SW_TUN_PROFID_IPV6_ESP;\n \t\t\t\telse if (ipv4_valid)\n-\t\t\t\t\treturn 0;\n+\t\t\t\t\tgoto inset_check;\n \t\t\t} else if (esp_spec && esp_mask &&\n \t\t\t\t\t\tesp_mask->hdr.spi){\n \t\t\t\tif (udp_valid)\n@@ -1247,7 +1141,7 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\t\t\tesp_spec->hdr.spi;\n \t\t\t\tlist[t].m_u.esp_hdr.spi =\n \t\t\t\t\tesp_mask->hdr.spi;\n-\t\t\t\tinput_set |= ICE_INSET_ESP_SPI;\n+\t\t\t\t*input |= ICE_INSET_ESP_SPI;\n \t\t\t\tinput_set_byte += 4;\n \t\t\t\tt++;\n \t\t\t}\n@@ -1273,7 +1167,7 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\t\t\t   RTE_FLOW_ERROR_TYPE_ITEM,\n \t\t\t\t\t   item,\n \t\t\t\t\t   \"Invalid ah item\");\n-\t\t\t\treturn 0;\n+\t\t\t\treturn false;\n \t\t\t}\n \t\t\t/* Check ah mask and update input set */\n \t\t\tif (ah_mask &&\n@@ -1285,10 +1179,11 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\t\t\t\tRTE_FLOW_ERROR_TYPE_ITEM,\n \t\t\t\t\t\titem,\n \t\t\t\t\t\t\"Invalid ah mask\");\n-\t\t\t\treturn 0;\n+\t\t\t\treturn false;\n \t\t\t}\n \n-\t\t\tif (!ah_spec && !ah_mask && !input_set) {\n+\t\t\tinput = &outer_input_set;\n+\t\t\tif (!ah_spec && !ah_mask && !(*input)) {\n \t\t\t\tprofile_rule = 1;\n \t\t\t\tif (ipv6_valid && udp_valid)\n \t\t\t\t\t*tun_type =\n@@ -1296,7 +1191,7 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\t\telse if (ipv6_valid)\n \t\t\t\t\t*tun_type = ICE_SW_TUN_PROFID_IPV6_AH;\n \t\t\t\telse if (ipv4_valid)\n-\t\t\t\t\treturn 0;\n+\t\t\t\t\tgoto inset_check;\n \t\t\t} else if (ah_spec && ah_mask &&\n \t\t\t\t\t\tah_mask->spi){\n \t\t\t\tlist[t].type = ICE_AH;\n@@ -1304,14 +1199,14 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\t\t\tah_spec->spi;\n \t\t\t\tlist[t].m_u.ah_hdr.spi =\n \t\t\t\t\tah_mask->spi;\n-\t\t\t\tinput_set |= ICE_INSET_AH_SPI;\n+\t\t\t\t*input |= ICE_INSET_AH_SPI;\n \t\t\t\tinput_set_byte += 4;\n \t\t\t\tt++;\n \t\t\t}\n \n \t\t\tif (!profile_rule) {\n \t\t\t\tif (udp_valid)\n-\t\t\t\t\treturn 0;\n+\t\t\t\t\tgoto inset_check;\n \t\t\t\telse if (ipv6_valid)\n \t\t\t\t\t*tun_type = ICE_SW_TUN_IPV6_AH;\n \t\t\t\telse if (ipv4_valid)\n@@ -1328,15 +1223,16 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\t\t\t   RTE_FLOW_ERROR_TYPE_ITEM,\n \t\t\t\t\t   item,\n \t\t\t\t\t   \"Invalid l2tp item\");\n-\t\t\t\treturn 0;\n+\t\t\t\treturn false;\n \t\t\t}\n \n-\t\t\tif (!l2tp_spec && !l2tp_mask && !input_set) {\n+\t\t\tinput = &outer_input_set;\n+\t\t\tif (!l2tp_spec && !l2tp_mask && !(*input)) {\n \t\t\t\tif (ipv6_valid)\n \t\t\t\t\t*tun_type =\n \t\t\t\t\tICE_SW_TUN_PROFID_MAC_IPV6_L2TPV3;\n \t\t\t\telse if (ipv4_valid)\n-\t\t\t\t\treturn 0;\n+\t\t\t\t\tgoto inset_check;\n \t\t\t} else if (l2tp_spec && l2tp_mask &&\n \t\t\t\t\t\tl2tp_mask->session_id){\n \t\t\t\tlist[t].type = ICE_L2TPV3;\n@@ -1344,7 +1240,7 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\t\t\tl2tp_spec->session_id;\n \t\t\t\tlist[t].m_u.l2tpv3_sess_hdr.session_id =\n \t\t\t\t\tl2tp_mask->session_id;\n-\t\t\t\tinput_set |= ICE_INSET_L2TPV3OIP_SESSION_ID;\n+\t\t\t\t*input |= ICE_INSET_L2TPV3OIP_SESSION_ID;\n \t\t\t\tinput_set_byte += 4;\n \t\t\t\tt++;\n \t\t\t}\n@@ -1372,7 +1268,7 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\t\t\t   RTE_FLOW_ERROR_TYPE_ITEM,\n \t\t\t\t\t   item,\n \t\t\t\t\t   \"Invalid PFCP item\");\n-\t\t\t\treturn -ENOTSUP;\n+\t\t\t\treturn false;\n \t\t\t}\n \t\t\tif (pfcp_spec && pfcp_mask) {\n \t\t\t\t/* Check pfcp mask and update input set */\n@@ -1383,7 +1279,7 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\t\t\t\tRTE_FLOW_ERROR_TYPE_ITEM,\n \t\t\t\t\t\titem,\n \t\t\t\t\t\t\"Invalid pfcp mask\");\n-\t\t\t\t\treturn -ENOTSUP;\n+\t\t\t\t\treturn false;\n \t\t\t\t}\n \t\t\t\tif (pfcp_mask->s_field &&\n \t\t\t\t\tpfcp_spec->s_field == 0x01 &&\n@@ -1404,7 +1300,7 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\t\t\t*tun_type =\n \t\t\t\t\tICE_SW_TUN_PROFID_IPV4_PFCP_NODE;\n \t\t\t\telse\n-\t\t\t\t\treturn -ENOTSUP;\n+\t\t\t\t\treturn false;\n \t\t\t}\n \t\t\tbreak;\n \n@@ -1416,7 +1312,7 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\t\t\tRTE_FLOW_ERROR_TYPE_ITEM,\n \t\t\t\t\titem,\n \t\t\t\t\t\"Invalid GTP item\");\n-\t\t\t\treturn 0;\n+\t\t\t\treturn false;\n \t\t\t}\n \t\t\tif (gtp_spec && gtp_mask) {\n \t\t\t\tif (gtp_mask->v_pt_rsv_flags ||\n@@ -1426,10 +1322,11 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\t\t\t\tRTE_FLOW_ERROR_TYPE_ITEM,\n \t\t\t\t\t\titem,\n \t\t\t\t\t\t\"Invalid GTP mask\");\n-\t\t\t\t\treturn 0;\n+\t\t\t\t\treturn false;\n \t\t\t\t}\n+\t\t\t\tinput = &outer_input_set;\n \t\t\t\tif (gtp_mask->teid)\n-\t\t\t\t\tinput_set |= ICE_INSET_GTPU_TEID;\n+\t\t\t\t\t*input |= ICE_INSET_GTPU_TEID;\n \t\t\t\tlist[t].type = ICE_GTP;\n \t\t\t\tlist[t].h_u.gtp_hdr.teid =\n \t\t\t\t\tgtp_spec->teid;\n@@ -1450,7 +1347,7 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\t\t\tRTE_FLOW_ERROR_TYPE_ITEM,\n \t\t\t\t\titem,\n \t\t\t\t\t\"Invalid GTPU_EH item\");\n-\t\t\t\treturn 0;\n+\t\t\t\treturn false;\n \t\t\t}\n \t\t\tif (gtp_psc_spec && gtp_psc_mask) {\n \t\t\t\tif (gtp_psc_mask->pdu_type) {\n@@ -1458,10 +1355,11 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\t\t\t\tRTE_FLOW_ERROR_TYPE_ITEM,\n \t\t\t\t\t\titem,\n \t\t\t\t\t\t\"Invalid GTPU_EH mask\");\n-\t\t\t\t\treturn 0;\n+\t\t\t\t\treturn false;\n \t\t\t\t}\n+\t\t\t\tinput = &outer_input_set;\n \t\t\t\tif (gtp_psc_mask->qfi)\n-\t\t\t\t\tinput_set |= ICE_INSET_GTPU_QFI;\n+\t\t\t\t\t*input |= ICE_INSET_GTPU_QFI;\n \t\t\t\tlist[t].type = ICE_GTP;\n \t\t\t\tlist[t].h_u.gtp_hdr.qfi =\n \t\t\t\t\tgtp_psc_spec->qfi;\n@@ -1480,7 +1378,7 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\trte_flow_error_set(error, EINVAL,\n \t\t\t\t   RTE_FLOW_ERROR_TYPE_ITEM, pattern,\n \t\t\t\t   \"Invalid pattern item.\");\n-\t\t\tgoto out;\n+\t\t\treturn false;\n \t\t}\n \t}\n \n@@ -1608,14 +1506,19 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\tRTE_FLOW_ERROR_TYPE_ITEM,\n \t\t\titem,\n \t\t\t\"too much input set\");\n-\t\treturn -ENOTSUP;\n+\t\treturn false;\n \t}\n \n \t*lkups_num = t;\n \n-\treturn input_set;\n-out:\n-\treturn 0;\n+inset_check:\n+\tif ((!outer_input_set && !inner_input_set &&\n+\t    !ice_is_prof_rule(*tun_type)) || (outer_input_set &\n+\t    ~pattern_match_item.input_set_mask_o) ||\n+\t    (inner_input_set & ~pattern_match_item.input_set_mask_i))\n+\t\treturn false;\n+\n+\treturn true;\n }\n \n static int\n@@ -1825,7 +1728,6 @@ ice_switch_parse_pattern_action(struct ice_adapter *ad,\n \t\tstruct rte_flow_error *error)\n {\n \tstruct ice_pf *pf = &ad->pf;\n-\tuint64_t inputset = 0;\n \tint ret = 0;\n \tstruct sw_meta *sw_meta_ptr = NULL;\n \tstruct ice_adv_rule_info rule_info;\n@@ -1892,10 +1794,8 @@ ice_switch_parse_pattern_action(struct ice_adapter *ad,\n \t\tgoto error;\n \t}\n \n-\tinputset = ice_switch_inset_get\n-\t\t(pattern, error, list, &lkups_num, &tun_type);\n-\tif ((!inputset && !ice_is_prof_rule(tun_type)) ||\n-\t\t(inputset & ~pattern_match_item->input_set_mask_o)) {\n+\tif (ice_switch_parse_pattern(pattern, error, list, &lkups_num,\n+\t\t\t\t   &tun_type, *pattern_match_item) == false) {\n \t\trte_flow_error_set(error, EINVAL,\n \t\t\t\t   RTE_FLOW_ERROR_TYPE_ITEM_SPEC,\n \t\t\t\t   pattern,\n",
    "prefixes": [
        "v2",
        "1/2"
    ]
}