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GET /api/patches/91963/?format=api
{ "id": 91963, "url": "http://patches.dpdk.org/api/patches/91963/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210421163441.17240-4-talshn@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210421163441.17240-4-talshn@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210421163441.17240-4-talshn@nvidia.com", "date": "2021-04-21T16:34:41", "name": "[3/3] net/mlx5: support checksum offload on Windows", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "723624e2cb2bfebc4b334abee084f460a428c806", "submitter": { "id": 1893, "url": "http://patches.dpdk.org/api/people/1893/?format=api", "name": "Tal Shnaiderman", "email": "talshn@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210421163441.17240-4-talshn@nvidia.com/mbox/", "series": [ { "id": 16572, "url": "http://patches.dpdk.org/api/series/16572/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16572", "date": "2021-04-21T16:34:39", "name": "mlx5 - support checksum offloads on Windows", "version": 1, "mbox": "http://patches.dpdk.org/series/16572/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/91963/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/91963/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A9EB0A0547;\n\tWed, 21 Apr 2021 18:35:30 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id C09F241B98;\n\tWed, 21 Apr 2021 18:35:17 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by mails.dpdk.org (Postfix) with ESMTP id 0DC8041B84\n for <dev@dpdk.org>; Wed, 21 Apr 2021 18:35:12 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n talshn@nvidia.com) with SMTP; 21 Apr 2021 19:35:11 +0300", "from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 13LGZBMf005314;\n Wed, 21 Apr 2021 19:35:11 +0300" ], "From": "Tal Shnaiderman <talshn@nvidia.com>", "To": "dev@dpdk.org", "Cc": "thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com,\n asafp@nvidia.com, odia@nvidia.com", "Date": "Wed, 21 Apr 2021 19:34:41 +0300", "Message-Id": "<20210421163441.17240-4-talshn@nvidia.com>", "X-Mailer": "git-send-email 2.16.1.windows.4", "In-Reply-To": "<20210421163441.17240-1-talshn@nvidia.com>", "References": "<20210421163441.17240-1-talshn@nvidia.com>", "Subject": "[dpdk-dev] [PATCH 3/3] net/mlx5: support checksum offload on Windows", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Support of the checksum offloading by checking\nthe relevant FW capability (csum_cap) for NIC support.\n\nRX supported offloads:\n\nDEV_RX_OFFLOAD_IPV4_CKSUM\nDEV_RX_OFFLOAD_UDP_CKSUM\nDEV_RX_OFFLOAD_TCP_CKSUM\n\nTX supported offloads:\n\nDEV_TX_OFFLOAD_IPV4_CKSUM\nDEV_TX_OFFLOAD_UDP_CKSUM\nDEV_TX_OFFLOAD_TCP_CKSUM\n\nSigned-off-by: Tal Shnaiderman <talshn@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/windows/mlx5_os.c | 5 +++--\n 1 file changed, 3 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c\nindex 5e53042b85..3fe3f55f49 100644\n--- a/drivers/net/mlx5/windows/mlx5_os.c\n+++ b/drivers/net/mlx5/windows/mlx5_os.c\n@@ -420,8 +420,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \terr = mlx5_dev_check_sibling_config(priv, config);\n \tif (err)\n \t\tgoto error;\n-\tDRV_LOG(DEBUG, \"checksum offloading is %ssupported\",\n-\t\t(config->hw_csum ? \"\" : \"not \"));\n \tDRV_LOG(DEBUG, \"counters are not supported\");\n \tconfig->ind_table_max_size =\n \t\tsh->device_attr.max_rwq_indirection_table_size;\n@@ -464,6 +462,9 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\t\tsh->cmng.relaxed_ordering_read =\n \t\t\t\tconfig->hca_attr.relaxed_ordering_read;\n \t\t}\n+\t\tconfig->hw_csum = config->hca_attr.csum_cap;\n+\t\tDRV_LOG(DEBUG, \"checksum offloading is %ssupported\",\n+\t\t (config->hw_csum ? \"\" : \"not \"));\n \t}\n \tif (config->devx) {\n \t\tuint32_t reg[MLX5_ST_SZ_DW(register_mtutc)];\n", "prefixes": [ "3/3" ] }