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GET /api/patches/91962/?format=api
{ "id": 91962, "url": "http://patches.dpdk.org/api/patches/91962/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210421163441.17240-3-talshn@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210421163441.17240-3-talshn@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210421163441.17240-3-talshn@nvidia.com", "date": "2021-04-21T16:34:40", "name": "[2/3] common/mlx5: read checksum capability from DevX", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "2fe6f688827b325ae25d55bcba85b7d5d522693d", "submitter": { "id": 1893, "url": "http://patches.dpdk.org/api/people/1893/?format=api", "name": "Tal Shnaiderman", "email": "talshn@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210421163441.17240-3-talshn@nvidia.com/mbox/", "series": [ { "id": 16572, "url": "http://patches.dpdk.org/api/series/16572/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16572", "date": "2021-04-21T16:34:39", "name": "mlx5 - support checksum offloads on Windows", "version": 1, "mbox": "http://patches.dpdk.org/series/16572/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/91962/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/91962/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 60D72A0547;\n\tWed, 21 Apr 2021 18:35:25 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 80D8641B93;\n\tWed, 21 Apr 2021 18:35:16 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by mails.dpdk.org (Postfix) with ESMTP id F05B94068A\n for <dev@dpdk.org>; Wed, 21 Apr 2021 18:35:12 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n talshn@nvidia.com) with SMTP; 21 Apr 2021 19:35:11 +0300", "from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 13LGZBMe005314;\n Wed, 21 Apr 2021 19:35:11 +0300" ], "From": "Tal Shnaiderman <talshn@nvidia.com>", "To": "dev@dpdk.org", "Cc": "thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com,\n asafp@nvidia.com, odia@nvidia.com", "Date": "Wed, 21 Apr 2021 19:34:40 +0300", "Message-Id": "<20210421163441.17240-3-talshn@nvidia.com>", "X-Mailer": "git-send-email 2.16.1.windows.4", "In-Reply-To": "<20210421163441.17240-1-talshn@nvidia.com>", "References": "<20210421163441.17240-1-talshn@nvidia.com>", "Subject": "[dpdk-dev] [PATCH 2/3] common/mlx5: read checksum capability from\n DevX", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "mlx5 in Windows needs the hca capability csum_cap\nto query the NIC for checksum offloading support\n\nAdded the capability as part of the capabilities\nqueried by the PMD using DevX.\n\nSigned-off-by: Tal Shnaiderman <talshn@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 2 ++\n drivers/common/mlx5/mlx5_devx_cmds.h | 1 +\n 2 files changed, 3 insertions(+)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 268bcd0d99..d2e4ab33a2 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -837,6 +837,8 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \thcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);\n \tattr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps,\n \t\t\t\t\t hcattr, wqe_vlan_insert);\n+\tattr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps,\n+\t\t\t\t\t hcattr, csum_cap);\n \tattr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,\n \t\t\t\t lro_cap);\n \tattr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex 67b5f771c6..1fb9130e51 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -92,6 +92,7 @@ struct mlx5_hca_attr {\n \tuint32_t eth_net_offloads:1;\n \tuint32_t eth_virt:1;\n \tuint32_t wqe_vlan_insert:1;\n+\tuint32_t csum_cap:1;\n \tuint32_t wqe_inline_mode:2;\n \tuint32_t vport_inline_mode:3;\n \tuint32_t tunnel_stateless_geneve_rx:1;\n", "prefixes": [ "2/3" ] }