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GET /api/patches/91960/?format=api
{ "id": 91960, "url": "http://patches.dpdk.org/api/patches/91960/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210421163441.17240-2-talshn@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210421163441.17240-2-talshn@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210421163441.17240-2-talshn@nvidia.com", "date": "2021-04-21T16:34:39", "name": "[1/3] net/mlx5: fix unsupported offloads disablement", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "091107a3652aff1d7ec323e28a46aedbaece7e35", "submitter": { "id": 1893, "url": "http://patches.dpdk.org/api/people/1893/?format=api", "name": "Tal Shnaiderman", "email": "talshn@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210421163441.17240-2-talshn@nvidia.com/mbox/", "series": [ { "id": 16572, "url": "http://patches.dpdk.org/api/series/16572/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16572", "date": "2021-04-21T16:34:39", "name": "mlx5 - support checksum offloads on Windows", "version": 1, "mbox": "http://patches.dpdk.org/series/16572/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/91960/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/91960/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1FFC7A0547;\n\tWed, 21 Apr 2021 18:35:14 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E1CE7410F9;\n\tWed, 21 Apr 2021 18:35:13 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by mails.dpdk.org (Postfix) with ESMTP id 0504041B82\n for <dev@dpdk.org>; Wed, 21 Apr 2021 18:35:12 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n talshn@nvidia.com) with SMTP; 21 Apr 2021 19:35:11 +0300", "from nvidia.com (l-wincomp04-vm.mtl.labs.mlnx [10.237.1.5])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 13LGZBMd005314;\n Wed, 21 Apr 2021 19:35:11 +0300" ], "From": "Tal Shnaiderman <talshn@nvidia.com>", "To": "dev@dpdk.org", "Cc": "thomas@monjalon.net, matan@nvidia.com, rasland@nvidia.com,\n asafp@nvidia.com, odia@nvidia.com, stable@dpdk.org", "Date": "Wed, 21 Apr 2021 19:34:39 +0300", "Message-Id": "<20210421163441.17240-2-talshn@nvidia.com>", "X-Mailer": "git-send-email 2.16.1.windows.4", "In-Reply-To": "<20210421163441.17240-1-talshn@nvidia.com>", "References": "<20210421163441.17240-1-talshn@nvidia.com>", "Subject": "[dpdk-dev] [PATCH 1/3] net/mlx5: fix unsupported offloads\n disablement", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "mlx5 offloads which are unsupported on Windows\nare currently disabled by checks with IBV/DV flags\nwhich are irrelevant to Windows.\n\nThe checks are removed until they are fully available.\n\nFixes: 93f4ece91a1f (\"net/mlx5: spawn ethdev ports on Windows\")\nCc: stable@dpdk.org\n\nSigned-off-by: Tal Shnaiderman <talshn@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/windows/mlx5_os.c | 15 +--------------\n 1 file changed, 1 insertion(+), 14 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c\nindex 814063b5ce..5e53042b85 100644\n--- a/drivers/net/mlx5/windows/mlx5_os.c\n+++ b/drivers/net/mlx5/windows/mlx5_os.c\n@@ -359,11 +359,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \tconfig->swp = 0;\n \tconfig->ind_table_max_size =\n \t\tsh->device_attr.max_rwq_indirection_table_size;\n-\tif (RTE_CACHE_LINE_SIZE == 128 &&\n-\t !(device_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))\n-\t\tcqe_comp = 0;\n-\telse\n-\t\tcqe_comp = 1;\n+\tcqe_comp = 0;\n \tconfig->cqe_comp = cqe_comp;\n \tDRV_LOG(DEBUG, \"tunnel offloading is not supported\");\n \tconfig->tunnel_en = 0;\n@@ -424,8 +420,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \terr = mlx5_dev_check_sibling_config(priv, config);\n \tif (err)\n \t\tgoto error;\n-\tconfig->hw_csum = !!(sh->device_attr.device_cap_flags_ex &\n-\t\t\t IBV_DEVICE_RAW_IP_CSUM);\n \tDRV_LOG(DEBUG, \"checksum offloading is %ssupported\",\n \t\t(config->hw_csum ? \"\" : \"not \"));\n \tDRV_LOG(DEBUG, \"counters are not supported\");\n@@ -439,19 +433,12 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\tconfig->ind_table_max_size = ETH_RSS_RETA_SIZE_512;\n \tDRV_LOG(DEBUG, \"maximum Rx indirection table size is %u\",\n \t\tconfig->ind_table_max_size);\n-\tconfig->hw_vlan_strip = !!(sh->device_attr.raw_packet_caps &\n-\t\t\t\t IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);\n \tDRV_LOG(DEBUG, \"VLAN stripping is %ssupported\",\n \t\t(config->hw_vlan_strip ? \"\" : \"not \"));\n-\tconfig->hw_fcs_strip = !!(sh->device_attr.raw_packet_caps &\n-\t\t\t\t IBV_RAW_PACKET_CAP_SCATTER_FCS);\n \tif (config->hw_padding) {\n \t\tDRV_LOG(DEBUG, \"Rx end alignment padding isn't supported\");\n \t\tconfig->hw_padding = 0;\n \t}\n-\tconfig->tso = (sh->device_attr.max_tso > 0 &&\n-\t\t (sh->device_attr.tso_supported_qpts &\n-\t\t (1 << IBV_QPT_RAW_PACKET)));\n \tif (config->tso)\n \t\tconfig->tso_max_payload_sz = sh->device_attr.max_tso;\n \tDRV_LOG(DEBUG, \"%sMPS is %s.\",\n", "prefixes": [ "1/3" ] }