Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/91870/?format=api
{ "id": 91870, "url": "http://patches.dpdk.org/api/patches/91870/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1618916122-181792-14-git-send-email-jiaweiw@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1618916122-181792-14-git-send-email-jiaweiw@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1618916122-181792-14-git-send-email-jiaweiw@nvidia.com", "date": "2021-04-20T10:55:20", "name": "[v6,13/15] net/mlx5: make ASO meter queue thread-safe", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "573de97bbf11fb85226500db3320c1c5353164e2", "submitter": { "id": 1939, "url": "http://patches.dpdk.org/api/people/1939/?format=api", "name": "Jiawei Wang", "email": "jiaweiw@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1618916122-181792-14-git-send-email-jiaweiw@nvidia.com/mbox/", "series": [ { "id": 16520, "url": "http://patches.dpdk.org/api/series/16520/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16520", "date": "2021-04-20T10:55:12", "name": "Add ASO meter support in MLX5 PMD", "version": 6, "mbox": "http://patches.dpdk.org/series/16520/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/91870/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/91870/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id BEFD2A0548;\n\tTue, 20 Apr 2021 12:56:34 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 29CB04177B;\n\tTue, 20 Apr 2021 12:55:42 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by mails.dpdk.org (Postfix) with ESMTP id A45BA41749\n for <dev@dpdk.org>; Tue, 20 Apr 2021 12:55:30 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n jiaweiw@nvidia.com) with SMTP; 20 Apr 2021 13:55:26 +0300", "from nvidia.com (gen-l-vrt-281.mtl.labs.mlnx [10.237.44.1])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 13KAtMS1009943;\n Tue, 20 Apr 2021 13:55:25 +0300" ], "From": "Jiawei Wang <jiaweiw@nvidia.com>", "To": "matan@nvidia.com, orika@nvidia.com, viacheslavo@nvidia.com,\n ferruh.yigit@intel.com, thomas@monjalon.net,\n Shahaf Shuler <shahafs@nvidia.com>", "Cc": "dev@dpdk.org, rasland@nvidia.com, asafp@nvidia.com,\n Li Zhang <lizh@nvidia.com>", "Date": "Tue, 20 Apr 2021 13:55:20 +0300", "Message-Id": "<1618916122-181792-14-git-send-email-jiaweiw@nvidia.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1618916122-181792-1-git-send-email-jiaweiw@nvidia.com>", "References": "<20210331073632.1443011-1-lizh@nvidia.com>\n <1618916122-181792-1-git-send-email-jiaweiw@nvidia.com>", "Subject": "[dpdk-dev] [PATCH v6 13/15] net/mlx5: make ASO meter queue\n thread-safe", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Li Zhang <lizh@nvidia.com>\n\nSynchronize ASO meter queue accesses from\ndifferent threads using a spinlock.\n\nSigned-off-by: Li Zhang <lizh@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/mlx5.h | 1 +\n drivers/net/mlx5/mlx5_flow_aso.c | 16 +++++++++++++---\n 2 files changed, 14 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex a045cf4..b2eb851 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -502,6 +502,7 @@ struct mlx5_aso_sq_elem {\n \n struct mlx5_aso_sq {\n \tuint16_t log_desc_n;\n+\trte_spinlock_t sqsl;\n \tstruct mlx5_aso_cq cq;\n \tstruct mlx5_devx_sq sq_obj;\n \tvolatile uint64_t *uar_addr;\ndiff --git a/drivers/net/mlx5/mlx5_flow_aso.c b/drivers/net/mlx5/mlx5_flow_aso.c\nindex fe5c991..cd2cc01 100644\n--- a/drivers/net/mlx5/mlx5_flow_aso.c\n+++ b/drivers/net/mlx5/mlx5_flow_aso.c\n@@ -274,6 +274,7 @@\n \tsq->tail = 0;\n \tsq->sqn = sq->sq_obj.sq->id;\n \tsq->uar_addr = mlx5_os_get_devx_uar_reg_addr(uar);\n+\trte_spinlock_init(&sq->sqsl);\n \treturn 0;\n error:\n \tmlx5_aso_destroy_sq(sq);\n@@ -665,12 +666,15 @@\n \tstruct mlx5_flow_meter_info *fm = NULL;\n \tuint16_t size = 1 << sq->log_desc_n;\n \tuint16_t mask = size - 1;\n-\tuint16_t res = size - (uint16_t)(sq->head - sq->tail);\n+\tuint16_t res;\n \tuint32_t dseg_idx = 0;\n \tstruct mlx5_aso_mtr_pool *pool = NULL;\n \n+\trte_spinlock_lock(&sq->sqsl);\n+\tres = size - (uint16_t)(sq->head - sq->tail);\n \tif (unlikely(!res)) {\n \t\tDRV_LOG(ERR, \"Fail: SQ is full and no free WQE to send\");\n+\t\trte_spinlock_unlock(&sq->sqsl);\n \t\treturn 0;\n \t}\n \twqe = &sq->sq_obj.aso_wqes[sq->head & mask];\n@@ -707,6 +711,7 @@\n \trte_wmb();\n \t*sq->uar_addr = *(volatile uint64_t *)wqe; /* Assume 64 bit ARCH. */\n \trte_wmb();\n+\trte_spinlock_unlock(&sq->sqsl);\n \treturn 1;\n }\n \n@@ -737,12 +742,16 @@\n \tconst unsigned int mask = cq_size - 1;\n \tuint32_t idx;\n \tuint32_t next_idx = cq->cq_ci & mask;\n-\tconst uint16_t max = (uint16_t)(sq->head - sq->tail);\n+\tuint16_t max;\n \tuint16_t n = 0;\n \tint ret;\n \n-\tif (unlikely(!max))\n+\trte_spinlock_lock(&sq->sqsl);\n+\tmax = (uint16_t)(sq->head - sq->tail);\n+\tif (unlikely(!max)) {\n+\t\trte_spinlock_unlock(&sq->sqsl);\n \t\treturn;\n+\t}\n \tdo {\n \t\tidx = next_idx;\n \t\tnext_idx = (cq->cq_ci + 1) & mask;\n@@ -769,6 +778,7 @@\n \t\trte_io_wmb();\n \t\tcq->cq_obj.db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);\n \t}\n+\trte_spinlock_unlock(&sq->sqsl);\n }\n \n /**\n", "prefixes": [ "v6", "13/15" ] }