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GET /api/patches/91229/?format=api
{ "id": 91229, "url": "http://patches.dpdk.org/api/patches/91229/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/66bbf891046aba887a2d5de20f26e0796887bb1f.1618309291.git.sthotton@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<66bbf891046aba887a2d5de20f26e0796887bb1f.1618309291.git.sthotton@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/66bbf891046aba887a2d5de20f26e0796887bb1f.1618309291.git.sthotton@marvell.com", "date": "2021-04-13T10:29:10", "name": "[v8,2/3] event/octeontx2: support crypto adapter forward mode", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "9171f9b4d9460ae7f0342bb5a9ba827b60b50c42", "submitter": { "id": 2049, "url": "http://patches.dpdk.org/api/people/2049/?format=api", "name": "Shijith Thotton", "email": "sthotton@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/66bbf891046aba887a2d5de20f26e0796887bb1f.1618309291.git.sthotton@marvell.com/mbox/", "series": [ { "id": 16330, "url": "http://patches.dpdk.org/api/series/16330/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16330", "date": "2021-04-13T10:29:08", "name": "Enhancements to crypto adapter forward mode", "version": 8, "mbox": "http://patches.dpdk.org/series/16330/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/91229/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/91229/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2A774A0524;\n\tTue, 13 Apr 2021 12:29:59 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 6109A160E12;\n\tTue, 13 Apr 2021 12:29:57 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 704E8160E11\n for <dev@dpdk.org>; Tue, 13 Apr 2021 12:29:55 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 13DALt4K009415; Tue, 13 Apr 2021 03:29:54 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com with ESMTP id 37w6vughrn-2\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Tue, 13 Apr 2021 03:29:54 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Tue, 13 Apr 2021 03:29:53 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Tue, 13 Apr 2021 03:29:53 -0700", "from localhost.localdomain (unknown [10.28.34.29])\n by maili.marvell.com (Postfix) with ESMTP id 7D9283F703F;\n Tue, 13 Apr 2021 03:29:48 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=AEIHg9SFQl+8xnil2nVlQTfS64X4DgakY6hLNOnLIpo=;\n b=fnMsL0ih9mHQi+kEtZxgMVdd4iSV8toOHEKRUf+dfJwOr+84XP85F8YFaWyBR2YNI2qB\n j7oIhvDDmWALltZu5ttczBjumwGkeStvgXw3Q/UZuX6yHb0arSByIIJtH9vp9fMPEWb+\n XMDfhc3ON6gwRP0uUzLDKDvTSSDXE/rbIQ7vWbAcGaeJQCMkphpazXBaXro2fr3Xm5uq\n 0hLbDE21yThLgDyJO0p424w3ZFkxt+m7tBHOjUkDz/LdrmjvcdJCbS60w01gXFQObYF9\n tgM/CBg0/wdsO66X3VBuTqoqV1UMyr3u7aZ81SqqnKdZzPwXRZwEVxYjEAOEawIdUtmm qA==", "From": "Shijith Thotton <sthotton@marvell.com>", "To": "<dev@dpdk.org>", "CC": "Shijith Thotton <sthotton@marvell.com>, <thomas@monjalon.net>,\n <jerinj@marvell.com>, <abhinandan.gujjar@intel.com>,\n <hemant.agrawal@nxp.com>, <nipun.gupta@nxp.com>,\n <sachin.saxena@oss.nxp.com>, <anoobj@marvell.com>, <matan@nvidia.com>,\n <roy.fan.zhang@intel.com>, <g.singh@nxp.com>,\n <erik.g.carrillo@intel.com>, <jay.jayatheerthan@intel.com>,\n <pbhagavatula@marvell.com>, <harry.van.haaren@intel.com>,\n Akhil Goyal <gakhil@marvell.com>", "Date": "Tue, 13 Apr 2021 15:59:10 +0530", "Message-ID": "\n <66bbf891046aba887a2d5de20f26e0796887bb1f.1618309291.git.sthotton@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<cover.1618309291.git.sthotton@marvell.com>", "References": "<cover.1618213226.git.sthotton@marvell.com>\n <cover.1618309291.git.sthotton@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "VyXgDeZIp1e34fy3jaAwWQGZDjgH1cUk", "X-Proofpoint-ORIG-GUID": "VyXgDeZIp1e34fy3jaAwWQGZDjgH1cUk", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761\n definitions=2021-04-13_04:2021-04-13,\n 2021-04-13 signatures=0", "Subject": "[dpdk-dev] [PATCH v8 2/3] event/octeontx2: support crypto adapter\n forward mode", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Advertise crypto adapter forward mode capability and set crypto adapter\nenqueue function in driver.\n\nSigned-off-by: Shijith Thotton <sthotton@marvell.com>\nAcked-by: Abhinandan Gujjar <abhinandan.gujjar@intel.com>\n---\n drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 49 +++++++----\n drivers/event/octeontx2/otx2_evdev.c | 5 +-\n .../event/octeontx2/otx2_evdev_crypto_adptr.c | 3 +-\n ...dptr_dp.h => otx2_evdev_crypto_adptr_rx.h} | 6 +-\n .../octeontx2/otx2_evdev_crypto_adptr_tx.h | 83 +++++++++++++++++++\n drivers/event/octeontx2/otx2_worker.h | 2 +-\n drivers/event/octeontx2/otx2_worker_dual.h | 2 +-\n 7 files changed, 129 insertions(+), 21 deletions(-)\n rename drivers/event/octeontx2/{otx2_evdev_crypto_adptr_dp.h => otx2_evdev_crypto_adptr_rx.h} (93%)\n create mode 100644 drivers/event/octeontx2/otx2_evdev_crypto_adptr_tx.h", "diff": "diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\nindex cec20b5c6..c918ed864 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\n@@ -7,6 +7,7 @@\n #include <rte_cryptodev_pmd.h>\n #include <rte_errno.h>\n #include <rte_ethdev.h>\n+#include <rte_event_crypto_adapter.h>\n \n #include \"otx2_cryptodev.h\"\n #include \"otx2_cryptodev_capabilities.h\"\n@@ -434,15 +435,35 @@ sym_session_configure(int driver_id, struct rte_crypto_sym_xform *xform,\n \treturn -ENOTSUP;\n }\n \n-static __rte_always_inline void __rte_hot\n+static __rte_always_inline int32_t __rte_hot\n otx2_ca_enqueue_req(const struct otx2_cpt_qp *qp,\n \t\t struct cpt_request_info *req,\n \t\t void *lmtline,\n+\t\t struct rte_crypto_op *op,\n \t\t uint64_t cpt_inst_w7)\n {\n+\tunion rte_event_crypto_metadata *m_data;\n \tunion cpt_inst_s inst;\n \tuint64_t lmt_status;\n \n+\tif (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) {\n+\t\tm_data = rte_cryptodev_sym_session_get_user_data(\n+\t\t\t\t\t\top->sym->session);\n+\t\tif (m_data == NULL) {\n+\t\t\trte_pktmbuf_free(op->sym->m_src);\n+\t\t\trte_crypto_op_free(op);\n+\t\t\trte_errno = EINVAL;\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t} else if (op->sess_type == RTE_CRYPTO_OP_SESSIONLESS &&\n+\t\t op->private_data_offset) {\n+\t\tm_data = (union rte_event_crypto_metadata *)\n+\t\t\t ((uint8_t *)op +\n+\t\t\t op->private_data_offset);\n+\t} else {\n+\t\treturn -EINVAL;\n+\t}\n+\n \tinst.u[0] = 0;\n \tinst.s9x.res_addr = req->comp_baddr;\n \tinst.u[2] = 0;\n@@ -453,12 +474,11 @@ otx2_ca_enqueue_req(const struct otx2_cpt_qp *qp,\n \tinst.s9x.ei2 = req->ist.ei2;\n \tinst.s9x.ei3 = cpt_inst_w7;\n \n-\tinst.s9x.qord = 1;\n-\tinst.s9x.grp = qp->ev.queue_id;\n-\tinst.s9x.tt = qp->ev.sched_type;\n-\tinst.s9x.tag = (RTE_EVENT_TYPE_CRYPTODEV << 28) |\n-\t\t\tqp->ev.flow_id;\n-\tinst.s9x.wq_ptr = (uint64_t)req >> 3;\n+\tinst.u[2] = (((RTE_EVENT_TYPE_CRYPTODEV << 28) |\n+\t\t m_data->response_info.flow_id) |\n+\t\t ((uint64_t)m_data->response_info.sched_type << 32) |\n+\t\t ((uint64_t)m_data->response_info.queue_id << 34));\n+\tinst.u[3] = 1 | (((uint64_t)req >> 3) << 3);\n \treq->qp = qp;\n \n \tdo {\n@@ -475,22 +495,22 @@ otx2_ca_enqueue_req(const struct otx2_cpt_qp *qp,\n \t\tlmt_status = otx2_lmt_submit(qp->lf_nq_reg);\n \t} while (lmt_status == 0);\n \n+\treturn 0;\n }\n \n static __rte_always_inline int32_t __rte_hot\n otx2_cpt_enqueue_req(const struct otx2_cpt_qp *qp,\n \t\t struct pending_queue *pend_q,\n \t\t struct cpt_request_info *req,\n+\t\t struct rte_crypto_op *op,\n \t\t uint64_t cpt_inst_w7)\n {\n \tvoid *lmtline = qp->lmtline;\n \tunion cpt_inst_s inst;\n \tuint64_t lmt_status;\n \n-\tif (qp->ca_enable) {\n-\t\totx2_ca_enqueue_req(qp, req, lmtline, cpt_inst_w7);\n-\t\treturn 0;\n-\t}\n+\tif (qp->ca_enable)\n+\t\treturn otx2_ca_enqueue_req(qp, req, lmtline, op, cpt_inst_w7);\n \n \tif (unlikely(pend_q->pending_count >= OTX2_CPT_DEFAULT_CMD_QLEN))\n \t\treturn -EAGAIN;\n@@ -594,7 +614,8 @@ otx2_cpt_enqueue_asym(struct otx2_cpt_qp *qp,\n \t\tgoto req_fail;\n \t}\n \n-\tret = otx2_cpt_enqueue_req(qp, pend_q, params.req, sess->cpt_inst_w7);\n+\tret = otx2_cpt_enqueue_req(qp, pend_q, params.req, op,\n+\t\t\t\t sess->cpt_inst_w7);\n \n \tif (unlikely(ret)) {\n \t\tCPT_LOG_DP_ERR(\"Could not enqueue crypto req\");\n@@ -638,7 +659,7 @@ otx2_cpt_enqueue_sym(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,\n \t\treturn ret;\n \t}\n \n-\tret = otx2_cpt_enqueue_req(qp, pend_q, req, sess->cpt_inst_w7);\n+\tret = otx2_cpt_enqueue_req(qp, pend_q, req, op, sess->cpt_inst_w7);\n \n \tif (unlikely(ret)) {\n \t\t/* Free buffer allocated by fill params routines */\n@@ -707,7 +728,7 @@ otx2_cpt_enqueue_sec(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,\n \t\treturn ret;\n \t}\n \n-\tret = otx2_cpt_enqueue_req(qp, pend_q, req, sess->cpt_inst_w7);\n+\tret = otx2_cpt_enqueue_req(qp, pend_q, req, op, sess->cpt_inst_w7);\n \n \tif (winsz && esn) {\n \t\tseq_in_sa = ((uint64_t)esn_hi << 32) | esn_low;\ndiff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c\nindex cdadbb2b2..ee7a6ad51 100644\n--- a/drivers/event/octeontx2/otx2_evdev.c\n+++ b/drivers/event/octeontx2/otx2_evdev.c\n@@ -12,8 +12,9 @@\n #include <rte_mbuf_pool_ops.h>\n #include <rte_pci.h>\n \n-#include \"otx2_evdev_stats.h\"\n #include \"otx2_evdev.h\"\n+#include \"otx2_evdev_crypto_adptr_tx.h\"\n+#include \"otx2_evdev_stats.h\"\n #include \"otx2_irq.h\"\n #include \"otx2_tim_evdev.h\"\n \n@@ -311,6 +312,7 @@ SSO_TX_ADPTR_ENQ_FASTPATH_FUNC\n \t\t\t[!!(dev->tx_offloads & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]\n \t\t\t[!!(dev->tx_offloads & NIX_TX_OFFLOAD_L3_L4_CSUM_F)];\n \t}\n+\tevent_dev->ca_enqueue = otx2_ssogws_ca_enq;\n \n \tif (dev->dual_ws) {\n \t\tevent_dev->enqueue\t\t= otx2_ssogws_dual_enq;\n@@ -473,6 +475,7 @@ SSO_TX_ADPTR_ENQ_FASTPATH_FUNC\n \t\t\t\t[!!(dev->tx_offloads &\n \t\t\t\t\t\tNIX_TX_OFFLOAD_L3_L4_CSUM_F)];\n \t\t}\n+\t\tevent_dev->ca_enqueue = otx2_ssogws_dual_ca_enq;\n \t}\n \n \tevent_dev->txa_enqueue_same_dest = event_dev->txa_enqueue;\ndiff --git a/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c b/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c\nindex 4e8a96cb6..2c9b347f0 100644\n--- a/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c\n+++ b/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c\n@@ -18,7 +18,8 @@ otx2_ca_caps_get(const struct rte_eventdev *dev,\n \tRTE_SET_USED(cdev);\n \n \t*caps = RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_QP_EV_BIND |\n-\t\tRTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_NEW;\n+\t\tRTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_NEW |\n+\t\tRTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_FWD;\n \n \treturn 0;\n }\ndiff --git a/drivers/event/octeontx2/otx2_evdev_crypto_adptr_dp.h b/drivers/event/octeontx2/otx2_evdev_crypto_adptr_rx.h\nsimilarity index 93%\nrename from drivers/event/octeontx2/otx2_evdev_crypto_adptr_dp.h\nrename to drivers/event/octeontx2/otx2_evdev_crypto_adptr_rx.h\nindex 70b63933e..9e331fdd7 100644\n--- a/drivers/event/octeontx2/otx2_evdev_crypto_adptr_dp.h\n+++ b/drivers/event/octeontx2/otx2_evdev_crypto_adptr_rx.h\n@@ -2,8 +2,8 @@\n * Copyright (C) 2020 Marvell International Ltd.\n */\n \n-#ifndef _OTX2_EVDEV_CRYPTO_ADPTR_DP_H_\n-#define _OTX2_EVDEV_CRYPTO_ADPTR_DP_H_\n+#ifndef _OTX2_EVDEV_CRYPTO_ADPTR_RX_H_\n+#define _OTX2_EVDEV_CRYPTO_ADPTR_RX_H_\n \n #include <rte_cryptodev.h>\n #include <rte_cryptodev_pmd.h>\n@@ -72,4 +72,4 @@ otx2_handle_crypto_event(uint64_t get_work1)\n \n \treturn (uint64_t)(cop);\n }\n-#endif /* _OTX2_EVDEV_CRYPTO_ADPTR_DP_H_ */\n+#endif /* _OTX2_EVDEV_CRYPTO_ADPTR_RX_H_ */\ndiff --git a/drivers/event/octeontx2/otx2_evdev_crypto_adptr_tx.h b/drivers/event/octeontx2/otx2_evdev_crypto_adptr_tx.h\nnew file mode 100644\nindex 000000000..ecf7eb9f5\n--- /dev/null\n+++ b/drivers/event/octeontx2/otx2_evdev_crypto_adptr_tx.h\n@@ -0,0 +1,83 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (C) 2021 Marvell International Ltd.\n+ */\n+\n+#ifndef _OTX2_EVDEV_CRYPTO_ADPTR_TX_H_\n+#define _OTX2_EVDEV_CRYPTO_ADPTR_TX_H_\n+\n+#include <rte_cryptodev.h>\n+#include <rte_cryptodev_pmd.h>\n+#include <rte_event_crypto_adapter.h>\n+#include <rte_eventdev.h>\n+\n+#include <otx2_cryptodev_qp.h>\n+#include <otx2_worker.h>\n+\n+static inline uint16_t\n+otx2_ca_enq(uintptr_t tag_op, const struct rte_event *ev)\n+{\n+\tunion rte_event_crypto_metadata *m_data;\n+\tstruct rte_crypto_op *crypto_op;\n+\tstruct rte_cryptodev *cdev;\n+\tstruct otx2_cpt_qp *qp;\n+\tuint8_t cdev_id;\n+\tuint16_t qp_id;\n+\n+\tcrypto_op = ev->event_ptr;\n+\tif (crypto_op == NULL)\n+\t\treturn 0;\n+\n+\tif (crypto_op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) {\n+\t\tm_data = rte_cryptodev_sym_session_get_user_data(\n+\t\t\t\t\t\tcrypto_op->sym->session);\n+\t\tif (m_data == NULL)\n+\t\t\tgoto free_op;\n+\n+\t\tcdev_id = m_data->request_info.cdev_id;\n+\t\tqp_id = m_data->request_info.queue_pair_id;\n+\t} else if (crypto_op->sess_type == RTE_CRYPTO_OP_SESSIONLESS &&\n+\t\t crypto_op->private_data_offset) {\n+\t\tm_data = (union rte_event_crypto_metadata *)\n+\t\t\t ((uint8_t *)crypto_op +\n+\t\t\t crypto_op->private_data_offset);\n+\t\tcdev_id = m_data->request_info.cdev_id;\n+\t\tqp_id = m_data->request_info.queue_pair_id;\n+\t} else {\n+\t\tgoto free_op;\n+\t}\n+\n+\tcdev = &rte_cryptodevs[cdev_id];\n+\tqp = cdev->data->queue_pairs[qp_id];\n+\n+\tif (!ev->sched_type)\n+\t\totx2_ssogws_head_wait(tag_op);\n+\tif (qp->ca_enable)\n+\t\treturn cdev->enqueue_burst(qp, &crypto_op, 1);\n+\n+free_op:\n+\trte_pktmbuf_free(crypto_op->sym->m_src);\n+\trte_crypto_op_free(crypto_op);\n+\trte_errno = EINVAL;\n+\treturn 0;\n+}\n+\n+static uint16_t __rte_hot\n+otx2_ssogws_ca_enq(void *port, struct rte_event ev[], uint16_t nb_events)\n+{\n+\tstruct otx2_ssogws *ws = port;\n+\n+\tRTE_SET_USED(nb_events);\n+\n+\treturn otx2_ca_enq(ws->tag_op, ev);\n+}\n+\n+static uint16_t __rte_hot\n+otx2_ssogws_dual_ca_enq(void *port, struct rte_event ev[], uint16_t nb_events)\n+{\n+\tstruct otx2_ssogws_dual *ws = port;\n+\n+\tRTE_SET_USED(nb_events);\n+\n+\treturn otx2_ca_enq(ws->ws_state[!ws->vws].tag_op, ev);\n+}\n+#endif /* _OTX2_EVDEV_CRYPTO_ADPTR_TX_H_ */\ndiff --git a/drivers/event/octeontx2/otx2_worker.h b/drivers/event/octeontx2/otx2_worker.h\nindex 2b716c042..fd149be91 100644\n--- a/drivers/event/octeontx2/otx2_worker.h\n+++ b/drivers/event/octeontx2/otx2_worker.h\n@@ -10,7 +10,7 @@\n \n #include <otx2_common.h>\n #include \"otx2_evdev.h\"\n-#include \"otx2_evdev_crypto_adptr_dp.h\"\n+#include \"otx2_evdev_crypto_adptr_rx.h\"\n #include \"otx2_ethdev_sec_tx.h\"\n \n /* SSO Operations */\ndiff --git a/drivers/event/octeontx2/otx2_worker_dual.h b/drivers/event/octeontx2/otx2_worker_dual.h\nindex 72b616439..36ae4dd88 100644\n--- a/drivers/event/octeontx2/otx2_worker_dual.h\n+++ b/drivers/event/octeontx2/otx2_worker_dual.h\n@@ -10,7 +10,7 @@\n \n #include <otx2_common.h>\n #include \"otx2_evdev.h\"\n-#include \"otx2_evdev_crypto_adptr_dp.h\"\n+#include \"otx2_evdev_crypto_adptr_rx.h\"\n \n /* SSO Operations */\n static __rte_always_inline uint16_t\n", "prefixes": [ "v8", "2/3" ] }