get:
Show a patch.

patch:
Update a patch.

put:
Update a patch.

GET /api/patches/91199/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 91199,
    "url": "http://patches.dpdk.org/api/patches/91199/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210413051459.4195-1-haiyue.wang@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20210413051459.4195-1-haiyue.wang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20210413051459.4195-1-haiyue.wang@intel.com",
    "date": "2021-04-13T05:14:59",
    "name": "[v1] net/ice: update QinQ switch filter handling",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "afc4c2a30f1920550e19c40e9790b9322e39a880",
    "submitter": {
        "id": 1044,
        "url": "http://patches.dpdk.org/api/people/1044/?format=api",
        "name": "Wang, Haiyue",
        "email": "haiyue.wang@intel.com"
    },
    "delegate": {
        "id": 1540,
        "url": "http://patches.dpdk.org/api/users/1540/?format=api",
        "username": "qzhan15",
        "first_name": "Qi",
        "last_name": "Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210413051459.4195-1-haiyue.wang@intel.com/mbox/",
    "series": [
        {
            "id": 16317,
            "url": "http://patches.dpdk.org/api/series/16317/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16317",
            "date": "2021-04-13T05:14:59",
            "name": "[v1] net/ice: update QinQ switch filter handling",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/16317/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/91199/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/91199/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 11D3CA0524;\n\tTue, 13 Apr 2021 07:34:05 +0200 (CEST)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 78A3D160B69;\n\tTue, 13 Apr 2021 07:34:05 +0200 (CEST)",
            "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n by mails.dpdk.org (Postfix) with ESMTP id 5550A160B61\n for <dev@dpdk.org>; Tue, 13 Apr 2021 07:34:04 +0200 (CEST)",
            "from orsmga008.jf.intel.com ([10.7.209.65])\n by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 12 Apr 2021 22:34:02 -0700",
            "from npg-dpdk-haiyue-1.sh.intel.com ([10.67.118.220])\n by orsmga008.jf.intel.com with ESMTP; 12 Apr 2021 22:34:01 -0700"
        ],
        "IronPort-SDR": [
            "\n YaWWGbtRcwLOcqRKeJBOdX/1LMWqfLooV2mh+FJSTZGhHslUsLiCUqDi4cUJVjFOFn1M/dcnlq\n g9svVwSkkZyQ==",
            "\n Z9e1JTgQrpxGSeQwHq7ReRQgoflZ/rtcPPWVcgjsSbnyOTapVYznKpa8zaPWa91AnxDPidVvso\n mJlahvsFazlg=="
        ],
        "X-IronPort-AV": [
            "E=McAfee;i=\"6200,9189,9952\"; a=\"258318340\"",
            "E=Sophos;i=\"5.82,218,1613462400\"; d=\"scan'208\";a=\"258318340\"",
            "E=Sophos;i=\"5.82,218,1613462400\"; d=\"scan'208\";a=\"424105182\""
        ],
        "X-ExtLoop1": "1",
        "From": "Haiyue Wang <haiyue.wang@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "qi.z.zhang@intel.com, Yuying.Zhang@intel.com,\n Haiyue Wang <haiyue.wang@intel.com>, Qiming Yang <qiming.yang@intel.com>",
        "Date": "Tue, 13 Apr 2021 13:14:59 +0800",
        "Message-Id": "<20210413051459.4195-1-haiyue.wang@intel.com>",
        "X-Mailer": "git-send-email 2.31.1",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Subject": "[dpdk-dev] [PATCH v1] net/ice: update QinQ switch filter handling",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "The hardware oueter/inner VLAN protocol types are now updated to map to\nnew interface VLAN protocol types, so update the application to use new\nVLAN protocol types when the rte_flow is QinQ filter type.\n\nSigned-off-by: Haiyue Wang <haiyue.wang@intel.com>\n---\nDepends-on: series-16315 (\"base code update batch 2\")\n---\n drivers/net/ice/ice_switch_filter.c | 36 ++++++++++++++++++-----------\n 1 file changed, 22 insertions(+), 14 deletions(-)",
    "diff": "diff --git a/drivers/net/ice/ice_switch_filter.c b/drivers/net/ice/ice_switch_filter.c\nindex 6f9e861d08..0bf3660677 100644\n--- a/drivers/net/ice/ice_switch_filter.c\n+++ b/drivers/net/ice/ice_switch_filter.c\n@@ -389,12 +389,17 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \tbool profile_rule = 0;\n \tbool nvgre_valid = 0;\n \tbool vxlan_valid = 0;\n+\tbool qinq_valid = 0;\n \tbool ipv6_valid = 0;\n \tbool ipv4_valid = 0;\n \tbool udp_valid = 0;\n \tbool tcp_valid = 0;\n \tuint16_t j, t = 0;\n \n+\tif (*tun_type == ICE_SW_TUN_AND_NON_TUN_QINQ ||\n+\t    *tun_type == ICE_NON_TUN_QINQ)\n+\t\tqinq_valid = 1;\n+\n \tfor (item = pattern; item->type !=\n \t\t\tRTE_FLOW_ITEM_TYPE_END; item++) {\n \t\tif (item->last) {\n@@ -932,22 +937,25 @@ ice_switch_inset_get(const struct rte_flow_item pattern[],\n \t\t\t\treturn 0;\n \t\t\t}\n \n-\t\t\tif (!outer_vlan_valid &&\n-\t\t\t    (*tun_type == ICE_SW_TUN_AND_NON_TUN_QINQ ||\n-\t\t\t     *tun_type == ICE_NON_TUN_QINQ))\n-\t\t\t\touter_vlan_valid = 1;\n-\t\t\telse if (!inner_vlan_valid &&\n-\t\t\t\t (*tun_type == ICE_SW_TUN_AND_NON_TUN_QINQ ||\n-\t\t\t\t  *tun_type == ICE_NON_TUN_QINQ))\n-\t\t\t\tinner_vlan_valid = 1;\n-\t\t\telse if (!inner_vlan_valid)\n-\t\t\t\tinner_vlan_valid = 1;\n+\t\t\tif (qinq_valid) {\n+\t\t\t\tif (!outer_vlan_valid)\n+\t\t\t\t\touter_vlan_valid = 1;\n+\t\t\t\telse\n+\t\t\t\t\tinner_vlan_valid = 1;\n+\t\t\t}\n \n \t\t\tif (vlan_spec && vlan_mask) {\n-\t\t\t\tif (outer_vlan_valid && !inner_vlan_valid) {\n-\t\t\t\t\tlist[t].type = ICE_VLAN_EX;\n-\t\t\t\t\tinput_set |= ICE_INSET_VLAN_OUTER;\n-\t\t\t\t} else if (inner_vlan_valid) {\n+\t\t\t\tif (qinq_valid) {\n+\t\t\t\t\tif (!inner_vlan_valid) {\n+\t\t\t\t\t\tlist[t].type = ICE_VLAN_EX;\n+\t\t\t\t\t\tinput_set |=\n+\t\t\t\t\t\t\tICE_INSET_VLAN_OUTER;\n+\t\t\t\t\t} else {\n+\t\t\t\t\t\tlist[t].type = ICE_VLAN_IN;\n+\t\t\t\t\t\tinput_set |=\n+\t\t\t\t\t\t\tICE_INSET_VLAN_INNER;\n+\t\t\t\t\t}\n+\t\t\t\t} else {\n \t\t\t\t\tlist[t].type = ICE_VLAN_OFOS;\n \t\t\t\t\tinput_set |= ICE_INSET_VLAN_INNER;\n \t\t\t\t}\n",
    "prefixes": [
        "v1"
    ]
}