Patch Detail

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{
    "id": 91128,
    "url": "http://patches.dpdk.org/api/patches/91128/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210413001033.1999355-3-lizh@nvidia.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20210413001033.1999355-3-lizh@nvidia.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20210413001033.1999355-3-lizh@nvidia.com",
    "date": "2021-04-13T00:10:20",
    "name": "[v3,02/14] common/mlx5: add color register idle bits definition",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "b1eb91b2514ed8c8513cb0128b2160ab3e703a5d",
    "submitter": {
        "id": 1967,
        "url": "http://patches.dpdk.org/api/people/1967/?format=api",
        "name": "Li Zhang",
        "email": "lizh@nvidia.com"
    },
    "delegate": {
        "id": 3268,
        "url": "http://patches.dpdk.org/api/users/3268/?format=api",
        "username": "rasland",
        "first_name": "Raslan",
        "last_name": "Darawsheh",
        "email": "rasland@nvidia.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210413001033.1999355-3-lizh@nvidia.com/mbox/",
    "series": [
        {
            "id": 16300,
            "url": "http://patches.dpdk.org/api/series/16300/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16300",
            "date": "2021-04-13T00:10:19",
            "name": "Add ASO meter support in MLX5 PMD",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/16300/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/91128/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/91128/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3E828A0524;\n\tTue, 13 Apr 2021 02:11:01 +0200 (CEST)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 087601608A9;\n\tTue, 13 Apr 2021 02:10:46 +0200 (CEST)",
            "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by mails.dpdk.org (Postfix) with ESMTP id 2A58116088D\n for <dev@dpdk.org>; Tue, 13 Apr 2021 02:10:40 +0200 (CEST)",
            "from Internal Mail-Server by MTLPINE1 (envelope-from\n lizh@nvidia.com)\n with SMTP; 13 Apr 2021 03:10:37 +0300",
            "from nvidia.com (c-235-17-1-009.mtl.labs.mlnx [10.235.17.9])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 13D0Abk7021795;\n Tue, 13 Apr 2021 03:10:37 +0300"
        ],
        "From": "Li Zhang <lizh@nvidia.com>",
        "To": "dekelp@nvidia.com, orika@nvidia.com, viacheslavo@nvidia.com,\n matan@nvidia.com, shahafs@nvidia.com",
        "Cc": "dev@dpdk.org, thomas@monjalon.net, rasland@nvidia.com, roniba@nvidia.com,\n Shun Hao <shunh@nvidia.com>",
        "Date": "Tue, 13 Apr 2021 03:10:20 +0300",
        "Message-Id": "<20210413001033.1999355-3-lizh@nvidia.com>",
        "X-Mailer": "git-send-email 2.21.0",
        "In-Reply-To": "<20210413001033.1999355-1-lizh@nvidia.com>",
        "References": "<20210331073632.1443011-1-lizh@nvidia.com>\n <20210413001033.1999355-1-lizh@nvidia.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Subject": "[dpdk-dev] [PATCH v3 02/14] common/mlx5: add color register idle\n bits definition",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Shun Hao <shunh@nvidia.com>\n\n8 bits are used for meter color in meter register. When the meter\nregister can be shared, the rest 24 bits can be used by others.\nThis adds the definination for the 24 bits that can be shared.\n\nSigned-off-by: Shun Hao <shunh@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/mlx5_prm.h | 6 ++++++\n 1 file changed, 6 insertions(+)",
    "diff": "diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 0ef0574f92..403ba80978 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -3382,6 +3382,12 @@ enum {\n /* The bits meter color use. */\n #define MLX5_MTR_COLOR_BITS 8\n \n+/* The bit size of one register. */\n+#define MLX5_REG_BITS 32\n+\n+/* Idle bits for non-color usage in color register. */\n+#define MLX5_MTR_IDLE_BITS_IN_COLOR_REG (MLX5_REG_BITS - MLX5_MTR_COLOR_BITS)\n+\n /* Length mode of dynamic flex parser graph node. */\n enum mlx5_parse_graph_node_len_mode {\n \tMLX5_GRAPH_NODE_LEN_FIXED = 0x0,\n",
    "prefixes": [
        "v3",
        "02/14"
    ]
}