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GET /api/patches/90661/?format=api
{ "id": 90661, "url": "http://patches.dpdk.org/api/patches/90661/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210406114131.25874-49-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210406114131.25874-49-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210406114131.25874-49-ndabilpuram@marvell.com", "date": "2021-04-06T11:41:27", "name": "[v4,48/52] common/cnxk: add sso irq support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "949c5548b8d59d33311986f9850db476a60d64db", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210406114131.25874-49-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 16128, "url": "http://patches.dpdk.org/api/series/16128/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16128", "date": "2021-04-06T11:40:39", "name": "Add Marvell CNXK common driver", "version": 4, "mbox": "http://patches.dpdk.org/series/16128/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/90661/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/90661/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 94033A0546;\n\tTue, 6 Apr 2021 13:49:06 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E2FDD1410BF;\n\tTue, 6 Apr 2021 13:44:07 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id A809F140F77\n for <dev@dpdk.org>; Tue, 6 Apr 2021 13:44:06 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 136Bdwfu008324 for <dev@dpdk.org>; Tue, 6 Apr 2021 04:44:05 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 37r72p2dw7-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 06 Apr 2021 04:44:05 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Tue, 6 Apr 2021 04:44:04 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Tue, 6 Apr 2021 04:44:04 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 03DE33F705E;\n Tue, 6 Apr 2021 04:44:01 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=2k4RUd2KWFsgkUs5ivv3GfS09sCD5HK7frQzBuxbKC0=;\n b=kUlATvr9CgIuZeIU/3wn+HUGr3f98hHA0qgJf0u2QyiM/wr6OkxJ7ouoPQAr8x/dDurY\n 8fNB1eLd1eBllPmunnLOKNEk/Wd8uzZoYONR11l3qHuOK1sq7BHUIyGsgPYLfS1bLecC\n ZQUFXDOKggkgv7QTLqLO16eY+3vw2Tph6LclkPS7UN6PxXeEWR9B9+rNmWGOVptbPlPB\n mLFJfsz2xuXrWquTRE+lC72I145KwLqv7E1nkCBnbvJHe9e9pcNiwhpL7d4ss2zh9e8F\n IeXWQPUyr8+OryLBoGxXGAb/yjSlxUGiCP+W5NdAbDSJYjs9EzeED6X1t4nFVERUzL01 ow==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>", "Date": "Tue, 6 Apr 2021 17:11:27 +0530", "Message-ID": "<20210406114131.25874-49-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210406114131.25874-1-ndabilpuram@marvell.com>", "References": "<20210305133918.8005-1-ndabilpuram@marvell.com>\n <20210406114131.25874-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "78GAtWBUWJICwhT1H4_bOwHyon_1KkwI", "X-Proofpoint-ORIG-GUID": "78GAtWBUWJICwhT1H4_bOwHyon_1KkwI", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-04-06_02:2021-04-01,\n 2021-04-06 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 48/52] common/cnxk: add sso irq support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd support to registering and un-registering SSO HWS and\nHWGRP IRQs.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/common/cnxk/meson.build | 1 +\n drivers/common/cnxk/roc_sso.c | 41 ++++++++++\n drivers/common/cnxk/roc_sso_irq.c | 164 +++++++++++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_sso_priv.h | 14 ++++\n 4 files changed, 220 insertions(+)\n create mode 100644 drivers/common/cnxk/roc_sso_irq.c", "diff": "diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build\nindex 79c8eaa..d28e273 100644\n--- a/drivers/common/cnxk/meson.build\n+++ b/drivers/common/cnxk/meson.build\n@@ -40,5 +40,6 @@ sources = files('roc_dev.c',\n \t\t'roc_npc_utils.c',\n \t\t'roc_platform.c',\n \t\t'roc_sso.c',\n+\t\t'roc_sso_irq.c',\n \t\t'roc_utils.c')\n includes += include_directories('../../bus/pci')\ndiff --git a/drivers/common/cnxk/roc_sso.c b/drivers/common/cnxk/roc_sso.c\nindex f4c4e5b..80d0320 100644\n--- a/drivers/common/cnxk/roc_sso.c\n+++ b/drivers/common/cnxk/roc_sso.c\n@@ -185,6 +185,27 @@ sso_hws_link_modify(uint8_t hws, uintptr_t base, struct plt_bitmap *bmp,\n \t}\n }\n \n+static int\n+sso_msix_fill(struct roc_sso *roc_sso, uint16_t nb_hws, uint16_t nb_hwgrp)\n+{\n+\tstruct sso *sso = roc_sso_to_sso_priv(roc_sso);\n+\tstruct msix_offset_rsp *rsp;\n+\tstruct dev *dev = &sso->dev;\n+\tint i, rc;\n+\n+\tmbox_alloc_msg_msix_offset(dev->mbox);\n+\trc = mbox_process_msg(dev->mbox, (void **)&rsp);\n+\tif (rc < 0)\n+\t\treturn rc;\n+\n+\tfor (i = 0; i < nb_hws; i++)\n+\t\tsso->hws_msix_offset[i] = rsp->ssow_msixoff[i];\n+\tfor (i = 0; i < nb_hwgrp; i++)\n+\t\tsso->hwgrp_msix_offset[i] = rsp->sso_msixoff[i];\n+\n+\treturn 0;\n+}\n+\n /* Public Functions. */\n uintptr_t\n roc_sso_hws_base_get(struct roc_sso *roc_sso, uint8_t hws)\n@@ -363,6 +384,7 @@ roc_sso_hwgrp_set_priority(struct roc_sso *roc_sso, uint16_t hwgrp,\n int\n roc_sso_rsrc_init(struct roc_sso *roc_sso, uint8_t nb_hws, uint16_t nb_hwgrp)\n {\n+\tstruct sso *sso = roc_sso_to_sso_priv(roc_sso);\n \tstruct sso_lf_alloc_rsp *rsp_hwgrp;\n \tint rc;\n \n@@ -400,10 +422,25 @@ roc_sso_rsrc_init(struct roc_sso *roc_sso, uint8_t nb_hws, uint16_t nb_hwgrp)\n \troc_sso->xae_waes = rsp_hwgrp->xaq_wq_entries;\n \troc_sso->iue = rsp_hwgrp->in_unit_entries;\n \n+\trc = sso_msix_fill(roc_sso, nb_hws, nb_hwgrp);\n+\tif (rc < 0) {\n+\t\tplt_err(\"Unable to get MSIX offsets for SSO LFs\");\n+\t\tgoto sso_msix_fail;\n+\t}\n+\n+\trc = sso_register_irqs_priv(roc_sso, &sso->pci_dev->intr_handle, nb_hws,\n+\t\t\t\t nb_hwgrp);\n+\tif (rc < 0) {\n+\t\tplt_err(\"Failed to register SSO LF IRQs\");\n+\t\tgoto sso_msix_fail;\n+\t}\n+\n \troc_sso->nb_hwgrp = nb_hwgrp;\n \troc_sso->nb_hws = nb_hws;\n \n \treturn 0;\n+sso_msix_fail:\n+\tsso_lf_free(roc_sso, SSO_LF_TYPE_HWGRP, nb_hwgrp);\n hwgrp_alloc_fail:\n \tsso_lf_free(roc_sso, SSO_LF_TYPE_HWS, nb_hws);\n hws_alloc_fail:\n@@ -416,9 +453,13 @@ roc_sso_rsrc_init(struct roc_sso *roc_sso, uint8_t nb_hws, uint16_t nb_hwgrp)\n void\n roc_sso_rsrc_fini(struct roc_sso *roc_sso)\n {\n+\tstruct sso *sso = roc_sso_to_sso_priv(roc_sso);\n+\n \tif (!roc_sso->nb_hws && !roc_sso->nb_hwgrp)\n \t\treturn;\n \n+\tsso_unregister_irqs_priv(roc_sso, &sso->pci_dev->intr_handle,\n+\t\t\t\t roc_sso->nb_hws, roc_sso->nb_hwgrp);\n \tsso_lf_free(roc_sso, SSO_LF_TYPE_HWS, roc_sso->nb_hws);\n \tsso_lf_free(roc_sso, SSO_LF_TYPE_HWGRP, roc_sso->nb_hwgrp);\n \ndiff --git a/drivers/common/cnxk/roc_sso_irq.c b/drivers/common/cnxk/roc_sso_irq.c\nnew file mode 100644\nindex 0000000..bf41482\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_sso_irq.c\n@@ -0,0 +1,164 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"roc_api.h\"\n+#include \"roc_priv.h\"\n+\n+static void\n+sso_hwgrp_irq(void *param)\n+{\n+\tstruct sso_rsrc *rsrc = param;\n+\tuint64_t intr;\n+\n+\tintr = plt_read64(rsrc->base + SSO_LF_GGRP_INT);\n+\tif (intr == 0)\n+\t\treturn;\n+\n+\tplt_err(\"GGRP %d GGRP_INT=0x%\" PRIx64 \"\", rsrc->rsrc_id, intr);\n+\n+\t/* Clear interrupt */\n+\tplt_write64(intr, rsrc->base + SSO_LF_GGRP_INT);\n+}\n+\n+static int\n+sso_hwgrp_register_irq(struct plt_intr_handle *handle, uint16_t ggrp_msixoff,\n+\t\t struct sso_rsrc *rsrc)\n+{\n+\tint rc, vec;\n+\n+\tvec = ggrp_msixoff + SSO_LF_INT_VEC_GRP;\n+\n+\t/* Clear err interrupt */\n+\tplt_write64(~0ull, rsrc->base + SSO_LF_GGRP_INT_ENA_W1C);\n+\t/* Set used interrupt vectors */\n+\trc = dev_irq_register(handle, sso_hwgrp_irq, (void *)rsrc, vec);\n+\t/* Enable hw interrupt */\n+\tplt_write64(~0ull, rsrc->base + SSO_LF_GGRP_INT_ENA_W1S);\n+\n+\treturn rc;\n+}\n+\n+static void\n+sso_hws_irq(void *param)\n+{\n+\tstruct sso_rsrc *rsrc = param;\n+\tuint64_t intr;\n+\n+\tintr = plt_read64(rsrc->base + SSOW_LF_GWS_INT);\n+\tif (intr == 0)\n+\t\treturn;\n+\n+\tplt_err(\"GWS %d GWS_INT=0x%\" PRIx64 \"\", rsrc->rsrc_id, intr);\n+\n+\t/* Clear interrupt */\n+\tplt_write64(intr, rsrc->base + SSOW_LF_GWS_INT);\n+}\n+\n+static int\n+sso_hws_register_irq(struct plt_intr_handle *handle, uint16_t hws_msixoff,\n+\t\t struct sso_rsrc *rsrc)\n+{\n+\tint rc, vec;\n+\n+\tvec = hws_msixoff + SSOW_LF_INT_VEC_IOP;\n+\n+\t/* Clear err interrupt */\n+\tplt_write64(~0ull, rsrc->base + SSOW_LF_GWS_INT_ENA_W1C);\n+\t/* Set used interrupt vectors */\n+\trc = dev_irq_register(handle, sso_hws_irq, (void *)rsrc, vec);\n+\t/* Enable hw interrupt */\n+\tplt_write64(~0ull, rsrc->base + SSOW_LF_GWS_INT_ENA_W1S);\n+\n+\treturn rc;\n+}\n+\n+int\n+sso_register_irqs_priv(struct roc_sso *roc_sso, struct plt_intr_handle *handle,\n+\t\t uint16_t nb_hws, uint16_t nb_hwgrp)\n+{\n+\tstruct sso *sso = roc_sso_to_sso_priv(roc_sso);\n+\tstruct dev *dev = &sso->dev;\n+\tint i, rc = SSO_ERR_PARAM;\n+\n+\tfor (i = 0; i < nb_hws; i++) {\n+\t\tif (sso->hws_msix_offset[i] == MSIX_VECTOR_INVALID) {\n+\t\t\tplt_err(\"Invalid SSO HWS MSIX offset[%d] vector 0x%x\",\n+\t\t\t\ti, sso->hws_msix_offset[i]);\n+\t\t\tgoto fail;\n+\t\t}\n+\t}\n+\n+\tfor (i = 0; i < nb_hwgrp; i++) {\n+\t\tif (sso->hwgrp_msix_offset[i] == MSIX_VECTOR_INVALID) {\n+\t\t\tplt_err(\"Invalid SSO HWGRP MSIX offset[%d] vector 0x%x\",\n+\t\t\t\ti, sso->hwgrp_msix_offset[i]);\n+\t\t\tgoto fail;\n+\t\t}\n+\t}\n+\n+\tfor (i = 0; i < nb_hws; i++) {\n+\t\tuintptr_t base =\n+\t\t\tdev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | i << 12);\n+\n+\t\tsso->hws_rsrc[i].rsrc_id = i;\n+\t\tsso->hws_rsrc[i].base = base;\n+\t\trc = sso_hws_register_irq(handle, sso->hws_msix_offset[i],\n+\t\t\t\t\t &sso->hws_rsrc[i]);\n+\t}\n+\n+\tfor (i = 0; i < nb_hwgrp; i++) {\n+\t\tuintptr_t base =\n+\t\t\tdev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 | i << 12);\n+\n+\t\tsso->hwgrp_rsrc[i].rsrc_id = i;\n+\t\tsso->hwgrp_rsrc[i].base = base;\n+\t\trc = sso_hwgrp_register_irq(handle, sso->hwgrp_msix_offset[i],\n+\t\t\t\t\t &sso->hwgrp_rsrc[i]);\n+\t}\n+fail:\n+\treturn rc;\n+}\n+\n+static void\n+sso_hwgrp_unregister_irq(struct plt_intr_handle *handle, uint16_t ggrp_msixoff,\n+\t\t\t struct sso_rsrc *rsrc)\n+{\n+\tint vec;\n+\n+\tvec = ggrp_msixoff + SSO_LF_INT_VEC_GRP;\n+\n+\t/* Clear err interrupt */\n+\tplt_write64(~0ull, rsrc->base + SSO_LF_GGRP_INT_ENA_W1C);\n+\tdev_irq_unregister(handle, sso_hwgrp_irq, (void *)rsrc, vec);\n+}\n+\n+static void\n+sso_hws_unregister_irq(struct plt_intr_handle *handle, uint16_t gws_msixoff,\n+\t\t struct sso_rsrc *rsrc)\n+{\n+\tint vec;\n+\n+\tvec = gws_msixoff + SSOW_LF_INT_VEC_IOP;\n+\n+\t/* Clear err interrupt */\n+\tplt_write64(~0ull, rsrc->base + SSOW_LF_GWS_INT_ENA_W1C);\n+\tdev_irq_unregister(handle, sso_hws_irq, (void *)rsrc, vec);\n+}\n+\n+void\n+sso_unregister_irqs_priv(struct roc_sso *roc_sso,\n+\t\t\t struct plt_intr_handle *handle, uint16_t nb_hws,\n+\t\t\t uint16_t nb_hwgrp)\n+{\n+\tstruct sso *sso = roc_sso_to_sso_priv(roc_sso);\n+\tint i;\n+\n+\tfor (i = 0; i < nb_hwgrp; i++)\n+\t\tsso_hwgrp_unregister_irq(handle, sso->hwgrp_msix_offset[i],\n+\t\t\t\t\t &sso->hwgrp_rsrc[i]);\n+\n+\tfor (i = 0; i < nb_hws; i++)\n+\t\tsso_hws_unregister_irq(handle, sso->hws_msix_offset[i],\n+\t\t\t\t &sso->hws_rsrc[i]);\n+}\ndiff --git a/drivers/common/cnxk/roc_sso_priv.h b/drivers/common/cnxk/roc_sso_priv.h\nindex ad35be1..5361d4f 100644\n--- a/drivers/common/cnxk/roc_sso_priv.h\n+++ b/drivers/common/cnxk/roc_sso_priv.h\n@@ -13,6 +13,12 @@ struct sso_rsrc {\n struct sso {\n \tstruct plt_pci_device *pci_dev;\n \tstruct dev dev;\n+\t/* Interrupt handler args. */\n+\tstruct sso_rsrc hws_rsrc[MAX_RVU_BLKLF_CNT];\n+\tstruct sso_rsrc hwgrp_rsrc[MAX_RVU_BLKLF_CNT];\n+\t/* MSIX offsets */\n+\tuint16_t hws_msix_offset[MAX_RVU_BLKLF_CNT];\n+\tuint16_t hwgrp_msix_offset[MAX_RVU_BLKLF_CNT];\n \t/* SSO link mapping. */\n \tstruct plt_bitmap **link_map;\n \tvoid *link_map_mem;\n@@ -33,4 +39,12 @@ roc_sso_to_sso_priv(struct roc_sso *roc_sso)\n \treturn (struct sso *)&roc_sso->reserved[0];\n }\n \n+/* SSO IRQ */\n+int sso_register_irqs_priv(struct roc_sso *roc_sso,\n+\t\t\t struct plt_intr_handle *handle, uint16_t nb_hws,\n+\t\t\t uint16_t nb_hwgrp);\n+void sso_unregister_irqs_priv(struct roc_sso *roc_sso,\n+\t\t\t struct plt_intr_handle *handle, uint16_t nb_hws,\n+\t\t\t uint16_t nb_hwgrp);\n+\n #endif /* _ROC_SSO_PRIV_H_ */\n", "prefixes": [ "v4", "48/52" ] }