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GET /api/patches/90638/?format=api
{ "id": 90638, "url": "http://patches.dpdk.org/api/patches/90638/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210406114131.25874-26-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210406114131.25874-26-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210406114131.25874-26-ndabilpuram@marvell.com", "date": "2021-04-06T11:41:04", "name": "[v4,25/52] common/cnxk: add nix ptp support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "32f6e77891ef1b0efd5662ba7b2e8096350e769e", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210406114131.25874-26-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 16128, "url": "http://patches.dpdk.org/api/series/16128/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16128", "date": "2021-04-06T11:40:39", "name": "Add Marvell CNXK common driver", "version": 4, "mbox": "http://patches.dpdk.org/series/16128/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/90638/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/90638/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 83E08A0546;\n\tTue, 6 Apr 2021 13:45:25 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 42D29140E55;\n\tTue, 6 Apr 2021 13:42:59 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id AD7EA140F5B\n for <dev@dpdk.org>; Tue, 6 Apr 2021 13:42:57 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 136BeRHn017503 for <dev@dpdk.org>; Tue, 6 Apr 2021 04:42:57 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 37redm9bhr-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 06 Apr 2021 04:42:57 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Tue, 6 Apr 2021 04:42:55 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Tue, 6 Apr 2021 04:42:55 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id AD8A13F703F;\n Tue, 6 Apr 2021 04:42:52 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=WgCBxkwOE2EXHUwF68ES9InVewMAAcaiKXrBJNGwkoM=;\n b=ajFk2Efo427LsNSolt/m3digzJuBGhETXCQe10oK/LTIYpyd3Le1NZbFLUWZE9jHjYWi\n 3cXpuGgNa0dY/Toc/aBg6oPFlUkXeosn9ruNBa6NrdJqy+WBxXIs4rCANygjkTEfbEWO\n x9uGhnxWsHhKHT/JXjV+ahT87HYIMT9Qqf/rTSjbN6xbDvyiUwjW8emI0/yzGnQQ/Lz6\n GI0C/zHbeS23MkAGphNPzLwIjQuZWwbA7l2G5Lq+z9iH6LD2ZOGLDL0LGiXWjgEIyBzk\n dWSk1SeYMVq1qv7gGLfcESxbyax8t8WvxfRTIjXqPppUFLNLze26uhRjCJmnGKmjARz3 Zw==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>", "Date": "Tue, 6 Apr 2021 17:11:04 +0530", "Message-ID": "<20210406114131.25874-26-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210406114131.25874-1-ndabilpuram@marvell.com>", "References": "<20210305133918.8005-1-ndabilpuram@marvell.com>\n <20210406114131.25874-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "j5lxZrkCkL36uQF-o8AgWA_RG0aYovx6", "X-Proofpoint-ORIG-GUID": "j5lxZrkCkL36uQF-o8AgWA_RG0aYovx6", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-04-06_02:2021-04-01,\n 2021-04-06 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 25/52] common/cnxk: add nix ptp support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Sunil Kumar Kori <skori@marvell.com>\n\nAdd support to enable/disable Rx and Tx PTP timestamping\nsupport. Also provide API's to register ptp info callbacks\nto get config change update from Kernel.\n\nSigned-off-by: Sunil Kumar Kori <skori@marvell.com>\n---\n drivers/common/cnxk/meson.build | 1 +\n drivers/common/cnxk/roc_nix.h | 16 +++++\n drivers/common/cnxk/roc_nix_ptp.c | 122 ++++++++++++++++++++++++++++++++++++++\n drivers/common/cnxk/version.map | 6 ++\n 4 files changed, 145 insertions(+)\n create mode 100644 drivers/common/cnxk/roc_nix_ptp.c", "diff": "diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build\nindex f6a8880..d01cf0b 100644\n--- a/drivers/common/cnxk/meson.build\n+++ b/drivers/common/cnxk/meson.build\n@@ -20,6 +20,7 @@ sources = files('roc_dev.c',\n \t\t'roc_nix_mac.c',\n \t\t'roc_nix_mcast.c',\n \t\t'roc_nix_npc.c',\n+\t\t'roc_nix_ptp.c',\n \t\t'roc_nix_queue.c',\n \t\t'roc_nix_rss.c',\n \t\t'roc_npa.c',\ndiff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex 83388ce..3cc1797 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -17,6 +17,11 @@ enum roc_nix_sq_max_sqe_sz {\n \troc_nix_maxsqesz_w8 = NIX_MAXSQESZ_W8,\n };\n \n+/* Range to adjust PTP frequency. Valid range is\n+ * (-ROC_NIX_PTP_FREQ_ADJUST, ROC_NIX_PTP_FREQ_ADJUST)\n+ */\n+#define ROC_NIX_PTP_FREQ_ADJUST (1 << 9)\n+\n /* NIX LF RX offload configuration flags.\n * These are input flags to roc_nix_lf_alloc:rx_cfg\n */\n@@ -244,6 +249,17 @@ int __roc_api roc_nix_cq_fini(struct roc_nix_cq *cq);\n int __roc_api roc_nix_sq_init(struct roc_nix *roc_nix, struct roc_nix_sq *sq);\n int __roc_api roc_nix_sq_fini(struct roc_nix_sq *sq);\n \n+/* PTP */\n+int __roc_api roc_nix_ptp_rx_ena_dis(struct roc_nix *roc_nix, int enable);\n+int __roc_api roc_nix_ptp_tx_ena_dis(struct roc_nix *roc_nix, int enable);\n+int __roc_api roc_nix_ptp_clock_read(struct roc_nix *roc_nix, uint64_t *clock,\n+\t\t\t\t uint64_t *tsc, uint8_t is_pmu);\n+int __roc_api roc_nix_ptp_sync_time_adjust(struct roc_nix *roc_nix,\n+\t\t\t\t\t int64_t delta);\n+int __roc_api roc_nix_ptp_info_cb_register(struct roc_nix *roc_nix,\n+\t\t\t\t\t ptp_info_update_t ptp_update);\n+void __roc_api roc_nix_ptp_info_cb_unregister(struct roc_nix *roc_nix);\n+\n /* MCAST*/\n int __roc_api roc_nix_mcast_mcam_entry_alloc(struct roc_nix *roc_nix,\n \t\t\t\t\t uint16_t nb_entries,\ndiff --git a/drivers/common/cnxk/roc_nix_ptp.c b/drivers/common/cnxk/roc_nix_ptp.c\nnew file mode 100644\nindex 0000000..03c4c6e\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_nix_ptp.c\n@@ -0,0 +1,122 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"roc_api.h\"\n+#include \"roc_priv.h\"\n+\n+#define PTP_FREQ_ADJUST (1 << 9)\n+\n+static inline struct mbox *\n+get_mbox(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\n+\treturn dev->mbox;\n+}\n+\n+int\n+roc_nix_ptp_rx_ena_dis(struct roc_nix *roc_nix, int enable)\n+{\n+\tstruct mbox *mbox = get_mbox(roc_nix);\n+\n+\tif (roc_nix_is_vf_or_sdp(roc_nix) || roc_nix_is_lbk(roc_nix))\n+\t\treturn NIX_ERR_PARAM;\n+\n+\tif (enable)\n+\t\tmbox_alloc_msg_cgx_ptp_rx_enable(mbox);\n+\telse\n+\t\tmbox_alloc_msg_cgx_ptp_rx_disable(mbox);\n+\n+\treturn mbox_process(mbox);\n+}\n+\n+int\n+roc_nix_ptp_tx_ena_dis(struct roc_nix *roc_nix, int enable)\n+{\n+\tstruct mbox *mbox = get_mbox(roc_nix);\n+\n+\tif (roc_nix_is_vf_or_sdp(roc_nix) || roc_nix_is_lbk(roc_nix))\n+\t\treturn NIX_ERR_PARAM;\n+\n+\tif (enable)\n+\t\tmbox_alloc_msg_nix_lf_ptp_tx_enable(mbox);\n+\telse\n+\t\tmbox_alloc_msg_nix_lf_ptp_tx_disable(mbox);\n+\n+\treturn mbox_process(mbox);\n+}\n+\n+int\n+roc_nix_ptp_clock_read(struct roc_nix *roc_nix, uint64_t *clock, uint64_t *tsc,\n+\t\t uint8_t is_pmu)\n+{\n+\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct ptp_req *req;\n+\tstruct ptp_rsp *rsp;\n+\tint rc = -ENOSPC;\n+\n+\treq = mbox_alloc_msg_ptp_op(mbox);\n+\tif (req == NULL)\n+\t\treturn rc;\n+\treq->op = PTP_OP_GET_CLOCK;\n+\treq->is_pmu = is_pmu;\n+\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tif (clock)\n+\t\t*clock = rsp->clk;\n+\n+\tif (tsc)\n+\t\t*tsc = rsp->tsc;\n+\n+\treturn 0;\n+}\n+\n+int\n+roc_nix_ptp_sync_time_adjust(struct roc_nix *roc_nix, int64_t delta)\n+{\n+\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct ptp_req *req;\n+\tstruct ptp_rsp *rsp;\n+\tint rc = -ENOSPC;\n+\n+\tif (roc_nix_is_vf_or_sdp(roc_nix) || roc_nix_is_lbk(roc_nix))\n+\t\treturn NIX_ERR_PARAM;\n+\n+\tif ((delta <= -PTP_FREQ_ADJUST) || (delta >= PTP_FREQ_ADJUST))\n+\t\treturn NIX_ERR_INVALID_RANGE;\n+\n+\treq = mbox_alloc_msg_ptp_op(mbox);\n+\tif (req == NULL)\n+\t\treturn rc;\n+\treq->op = PTP_OP_ADJFINE;\n+\treq->scaled_ppm = delta;\n+\n+\treturn mbox_process_msg(mbox, (void *)&rsp);\n+}\n+\n+int\n+roc_nix_ptp_info_cb_register(struct roc_nix *roc_nix,\n+\t\t\t ptp_info_update_t ptp_update)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\n+\tif (ptp_update == NULL)\n+\t\treturn NIX_ERR_PARAM;\n+\n+\tdev->ops->ptp_info_update = (ptp_info_t)ptp_update;\n+\treturn 0;\n+}\n+\n+void\n+roc_nix_ptp_info_cb_unregister(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\n+\tdev->ops->ptp_info_update = NULL;\n+}\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 3196738..2267cf7 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -55,6 +55,12 @@ INTERNAL {\n \troc_nix_npc_promisc_ena_dis;\n \troc_nix_npc_rx_ena_dis;\n \troc_nix_npc_mcast_config;\n+\troc_nix_ptp_clock_read;\n+\troc_nix_ptp_info_cb_register;\n+\troc_nix_ptp_info_cb_unregister;\n+\troc_nix_ptp_rx_ena_dis;\n+\troc_nix_ptp_sync_time_adjust;\n+\troc_nix_ptp_tx_ena_dis;\n \troc_nix_ras_intr_ena_dis;\n \troc_nix_register_cq_irqs;\n \troc_nix_register_queue_irqs;\n", "prefixes": [ "v4", "25/52" ] }