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GET /api/patches/90629/?format=api
{ "id": 90629, "url": "http://patches.dpdk.org/api/patches/90629/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210406114131.25874-17-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210406114131.25874-17-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210406114131.25874-17-ndabilpuram@marvell.com", "date": "2021-04-06T11:40:55", "name": "[v4,16/52] common/cnxk: add npa batch alloc/free support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "67bb0c7a220b2846c501a9d7d04ce5e333941d1c", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210406114131.25874-17-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 16128, "url": "http://patches.dpdk.org/api/series/16128/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16128", "date": "2021-04-06T11:40:39", "name": "Add Marvell CNXK common driver", "version": 4, "mbox": "http://patches.dpdk.org/series/16128/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/90629/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/90629/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E8CBEA0546;\n\tTue, 6 Apr 2021 13:44:10 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 5C14F140FA4;\n\tTue, 6 Apr 2021 13:42:30 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 6496F140E32\n for <dev@dpdk.org>; Tue, 6 Apr 2021 13:42:29 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 136Bep2o018536 for <dev@dpdk.org>; Tue, 6 Apr 2021 04:42:28 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 37redm9bfv-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 06 Apr 2021 04:42:28 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Tue, 6 Apr 2021 04:42:26 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Tue, 6 Apr 2021 04:42:27 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 4B22D3F703F;\n Tue, 6 Apr 2021 04:42:24 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=TQbyUhEJ944Lwy+XXCAC17MRUls3OX7S95mZnBOJLgo=;\n b=HAEPWSRx8uABbiBqltqLEbS/3O+fRXkyQCAMrFDHhLcfT9KXRBBRxQzcmC6yseqLZz29\n XwgoZ52r4A5VQlvct+zn9SlSQC4gUzyr7cZaB+uq34/SYNlSOwpvOX9e/WqxruU37I+l\n i6ua3XFGn7CuE8b4wgsiY6OcwIa3jHo9iQpQ6WmUXTSDSz4ZA3U2W5jf71/ws/3aH++A\n WpKDm51g1VBouMa6g4ovJkuv0c00CFq2iN58wi1d1KVwd62onvoJq8hyIqNfi3F586Tm\n P2vFglYUhl5zh/Dlsa/4a8Jeg5MPC5iobAHhqlTiUVIAbGq3BUKnRP73enwkahfph437 XQ==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>", "Date": "Tue, 6 Apr 2021 17:10:55 +0530", "Message-ID": "<20210406114131.25874-17-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210406114131.25874-1-ndabilpuram@marvell.com>", "References": "<20210305133918.8005-1-ndabilpuram@marvell.com>\n <20210406114131.25874-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "yolvYuDHJGcYQ4fRxD2eBRxuXDR5bmhq", "X-Proofpoint-ORIG-GUID": "yolvYuDHJGcYQ4fRxD2eBRxuXDR5bmhq", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-04-06_02:2021-04-01,\n 2021-04-06 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 16/52] common/cnxk: add npa batch alloc/free\n support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Ashwin Sekhar T K <asekhar@marvell.com>\n\nAdd APIs to do allocations/frees in batch from\nNPA pool.\n\nSigned-off-by: Ashwin Sekhar T K <asekhar@marvell.com>\n---\n drivers/common/cnxk/roc_npa.h | 217 ++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 217 insertions(+)", "diff": "diff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h\nindex 7c6f78d..89f5c6f 100644\n--- a/drivers/common/cnxk/roc_npa.h\n+++ b/drivers/common/cnxk/roc_npa.h\n@@ -8,6 +8,9 @@\n #define ROC_AURA_ID_MASK (BIT_ULL(16) - 1)\n #define ROC_AURA_OP_LIMIT_MASK (BIT_ULL(36) - 1)\n \n+#define ROC_CN10K_NPA_BATCH_ALLOC_MAX_PTRS 512\n+#define ROC_CN10K_NPA_BATCH_FREE_MAX_PTRS 15\n+\n /* 16 CASP instructions can be outstanding in CN9k, but we use only 15\n * outstanding CASPs as we run out of registers.\n */\n@@ -180,6 +183,114 @@ roc_npa_pool_op_performance_counter(uint64_t aura_handle, const int drop)\n \t\treturn reg & 0xFFFFFFFFFFFF;\n }\n \n+static inline int\n+roc_npa_aura_batch_alloc_issue(uint64_t aura_handle, uint64_t *buf,\n+\t\t\t unsigned int num, const int dis_wait,\n+\t\t\t const int drop)\n+{\n+\tunsigned int i;\n+\tint64_t *addr;\n+\tuint64_t res;\n+\tunion {\n+\t\tuint64_t u;\n+\t\tstruct npa_batch_alloc_compare_s compare_s;\n+\t} cmp;\n+\n+\tif (num > ROC_CN10K_NPA_BATCH_ALLOC_MAX_PTRS)\n+\t\treturn -1;\n+\n+\t/* Zero first word of every cache line */\n+\tfor (i = 0; i < num; i += (ROC_ALIGN / sizeof(uint64_t)))\n+\t\tbuf[i] = 0;\n+\n+\taddr = (int64_t *)(roc_npa_aura_handle_to_base(aura_handle) +\n+\t\t\t NPA_LF_AURA_BATCH_ALLOC);\n+\tcmp.u = 0;\n+\tcmp.compare_s.aura = roc_npa_aura_handle_to_aura(aura_handle);\n+\tcmp.compare_s.drop = drop;\n+\tcmp.compare_s.stype = ALLOC_STYPE_STSTP;\n+\tcmp.compare_s.dis_wait = dis_wait;\n+\tcmp.compare_s.count = num;\n+\n+\tres = roc_atomic64_cas(cmp.u, (uint64_t)buf, addr);\n+\tif (res != ALLOC_RESULT_ACCEPTED && res != ALLOC_RESULT_NOCORE)\n+\t\treturn -1;\n+\n+\treturn 0;\n+}\n+\n+static inline unsigned int\n+roc_npa_aura_batch_alloc_count(uint64_t *aligned_buf, unsigned int num)\n+{\n+\tunsigned int count, i;\n+\n+\tif (num > ROC_CN10K_NPA_BATCH_ALLOC_MAX_PTRS)\n+\t\treturn 0;\n+\n+\tcount = 0;\n+\t/* Check each ROC cache line one by one */\n+\tfor (i = 0; i < num; i += (ROC_ALIGN >> 3)) {\n+\t\tstruct npa_batch_alloc_status_s *status;\n+\t\tint ccode;\n+\n+\t\tstatus = (struct npa_batch_alloc_status_s *)&aligned_buf[i];\n+\n+\t\t/* Status is updated in first 7 bits of each 128 byte cache\n+\t\t * line. Wait until the status gets updated.\n+\t\t */\n+\t\tdo {\n+\t\t\tccode = (volatile int)status->ccode;\n+\t\t} while (ccode == ALLOC_CCODE_INVAL);\n+\n+\t\tcount += status->count;\n+\t}\n+\n+\treturn count;\n+}\n+\n+static inline unsigned int\n+roc_npa_aura_batch_alloc_extract(uint64_t *buf, uint64_t *aligned_buf,\n+\t\t\t\t unsigned int num)\n+{\n+\tunsigned int count, i;\n+\n+\tif (num > ROC_CN10K_NPA_BATCH_ALLOC_MAX_PTRS)\n+\t\treturn 0;\n+\n+\tcount = 0;\n+\t/* Check each ROC cache line one by one */\n+\tfor (i = 0; i < num; i += (ROC_ALIGN >> 3)) {\n+\t\tstruct npa_batch_alloc_status_s *status;\n+\t\tint line_count, ccode;\n+\n+\t\tstatus = (struct npa_batch_alloc_status_s *)&aligned_buf[i];\n+\n+\t\t/* Status is updated in first 7 bits of each 128 byte cache\n+\t\t * line. Wait until the status gets updated.\n+\t\t */\n+\t\tdo {\n+\t\t\tccode = (volatile int)status->ccode;\n+\t\t} while (ccode == ALLOC_CCODE_INVAL);\n+\n+\t\tline_count = status->count;\n+\n+\t\t/* Clear the status from the cache line */\n+\t\tstatus->ccode = 0;\n+\t\tstatus->count = 0;\n+\n+\t\t/* 'Compress' the allocated buffers as there can\n+\t\t * be 'holes' at the end of the 128 byte cache\n+\t\t * lines.\n+\t\t */\n+\t\tmemmove(&buf[count], &aligned_buf[i],\n+\t\t\tline_count * sizeof(uint64_t));\n+\n+\t\tcount += line_count;\n+\t}\n+\n+\treturn count;\n+}\n+\n static inline void\n roc_npa_aura_op_bulk_free(uint64_t aura_handle, uint64_t const *buf,\n \t\t\t unsigned int num, const int fabs)\n@@ -194,6 +305,112 @@ roc_npa_aura_op_bulk_free(uint64_t aura_handle, uint64_t const *buf,\n }\n \n static inline unsigned int\n+roc_npa_aura_op_batch_alloc(uint64_t aura_handle, uint64_t *buf,\n+\t\t\t uint64_t *aligned_buf, unsigned int num,\n+\t\t\t const int dis_wait, const int drop,\n+\t\t\t const int partial)\n+{\n+\tunsigned int count, chunk, num_alloc;\n+\n+\t/* The buffer should be 128 byte cache line aligned */\n+\tif (((uint64_t)aligned_buf & (ROC_ALIGN - 1)) != 0)\n+\t\treturn 0;\n+\n+\tcount = 0;\n+\twhile (num) {\n+\t\tchunk = (num > ROC_CN10K_NPA_BATCH_ALLOC_MAX_PTRS) ?\n+\t\t\t\t ROC_CN10K_NPA_BATCH_ALLOC_MAX_PTRS :\n+\t\t\t\t num;\n+\n+\t\tif (roc_npa_aura_batch_alloc_issue(aura_handle, aligned_buf,\n+\t\t\t\t\t\t chunk, dis_wait, drop))\n+\t\t\tbreak;\n+\n+\t\tnum_alloc = roc_npa_aura_batch_alloc_extract(buf, aligned_buf,\n+\t\t\t\t\t\t\t chunk);\n+\n+\t\tcount += num_alloc;\n+\t\tbuf += num_alloc;\n+\t\tnum -= num_alloc;\n+\n+\t\tif (num_alloc != chunk)\n+\t\t\tbreak;\n+\t}\n+\n+\t/* If the requested number of pointers was not allocated and if partial\n+\t * alloc is not desired, then free allocated pointers.\n+\t */\n+\tif (unlikely(num != 0 && !partial)) {\n+\t\troc_npa_aura_op_bulk_free(aura_handle, buf - count, count, 1);\n+\t\tcount = 0;\n+\t}\n+\n+\treturn count;\n+}\n+\n+static inline void\n+roc_npa_aura_batch_free(uint64_t aura_handle, uint64_t const *buf,\n+\t\t\tunsigned int num, const int fabs, uint64_t lmt_addr,\n+\t\t\tuint64_t lmt_id)\n+{\n+\tuint64_t addr, tar_addr, free0;\n+\tvolatile uint64_t *lmt_data;\n+\tunsigned int i;\n+\n+\tif (num > ROC_CN10K_NPA_BATCH_FREE_MAX_PTRS)\n+\t\treturn;\n+\n+\tlmt_data = (uint64_t *)lmt_addr;\n+\n+\taddr = roc_npa_aura_handle_to_base(aura_handle) +\n+\t NPA_LF_AURA_BATCH_FREE0;\n+\n+\t/*\n+\t * NPA_LF_AURA_BATCH_FREE0\n+\t *\n+\t * 63 63 62 33 32 32 31 20 19 0\n+\t * -----------------------------------------\n+\t * | FABS | Rsvd | COUNT_EOT | Rsvd | AURA |\n+\t * -----------------------------------------\n+\t */\n+\tfree0 = roc_npa_aura_handle_to_aura(aura_handle);\n+\tif (fabs)\n+\t\tfree0 |= (0x1UL << 63);\n+\tif (num & 0x1)\n+\t\tfree0 |= (0x1UL << 32);\n+\n+\t/* tar_addr[4:6] is LMTST size-1 in units of 128b */\n+\ttar_addr = addr | ((num >> 1) << 4);\n+\n+\tlmt_data[0] = free0;\n+\tfor (i = 0; i < num; i++)\n+\t\tlmt_data[i + 1] = buf[i];\n+\n+\troc_lmt_submit_steorl(lmt_id, tar_addr);\n+\tplt_io_wmb();\n+}\n+\n+static inline void\n+roc_npa_aura_op_batch_free(uint64_t aura_handle, uint64_t const *buf,\n+\t\t\t unsigned int num, const int fabs, uint64_t lmt_addr,\n+\t\t\t uint64_t lmt_id)\n+{\n+\tunsigned int chunk;\n+\n+\twhile (num) {\n+\t\tchunk = (num >= ROC_CN10K_NPA_BATCH_FREE_MAX_PTRS) ?\n+\t\t\t\t ROC_CN10K_NPA_BATCH_FREE_MAX_PTRS :\n+\t\t\t\t num;\n+\n+\t\troc_npa_aura_batch_free(aura_handle, buf, chunk, fabs, lmt_addr,\n+\t\t\t\t\tlmt_id);\n+\n+\t\tbuf += chunk;\n+\t\tnum -= chunk;\n+\t}\n+}\n+\n+static inline unsigned int\n roc_npa_aura_bulk_alloc(uint64_t aura_handle, uint64_t *buf, unsigned int num,\n \t\t\tconst int drop)\n {\n", "prefixes": [ "v4", "16/52" ] }