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GET /api/patches/90538/?format=api
{ "id": 90538, "url": "http://patches.dpdk.org/api/patches/90538/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210404074552.24190-3-rasland@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210404074552.24190-3-rasland@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210404074552.24190-3-rasland@nvidia.com", "date": "2021-04-04T07:45:52", "name": "[v4,2/2] ethdev: update qfi definition", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "e80da9efa093d647093818ae656a28b75ac16579", "submitter": { "id": 1868, "url": "http://patches.dpdk.org/api/people/1868/?format=api", "name": "Raslan Darawsheh", "email": "rasland@nvidia.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210404074552.24190-3-rasland@nvidia.com/mbox/", "series": [ { "id": 16096, "url": "http://patches.dpdk.org/api/series/16096/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16096", "date": "2021-04-04T07:45:50", "name": "fix gtp psc qfi support", "version": 4, "mbox": "http://patches.dpdk.org/series/16096/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/90538/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/90538/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id AE719A0547;\n\tSun, 4 Apr 2021 09:46:19 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 6CDF5140E97;\n\tSun, 4 Apr 2021 09:46:19 +0200 (CEST)", "from NAM12-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam12on2040.outbound.protection.outlook.com [40.107.243.40])\n by mails.dpdk.org (Postfix) with ESMTP id A0F7B140E81;\n Sun, 4 Apr 2021 09:46:18 +0200 (CEST)", "from MWHPR22CA0067.namprd22.prod.outlook.com (2603:10b6:300:12a::29)\n by BYAPR12MB3286.namprd12.prod.outlook.com (2603:10b6:a03:139::15)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3999.29; 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intel.com; dkim=none (message not signed)\n header.d=none;intel.com; dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "Raslan Darawsheh <rasland@nvidia.com>", "To": "<dev@dpdk.org>, <ferruh.yigit@intel.com>", "CC": "<orika@nvidia.com>, <andrew.rybchenko@oktetlabs.ru>,\n <ivan.malov@oktetlabs.ru>, <ying.a.wang@intel.com>, <olivier.matz@6wind.com>,\n <viacheslavo@nvidia.com>, <shirik@nvidia.com>, <stable@dpdk.org>", "Date": "Sun, 4 Apr 2021 10:45:52 +0300", "Message-ID": "<20210404074552.24190-3-rasland@nvidia.com>", "X-Mailer": "git-send-email 2.29.0", "In-Reply-To": "<20210404074552.24190-1-rasland@nvidia.com>", "References": "<20210330075036.6579-2-rasland@nvidia.com>\n <20210404074552.24190-1-rasland@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.145.6]", "X-ClientProxiedBy": "HQMAIL111.nvidia.com (172.20.187.18) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "f0a2234f-79af-4c25-fb9c-08d8f73dbab0", "X-MS-TrafficTypeDiagnostic": "BYAPR12MB3286:", "X-Microsoft-Antispam-PRVS": "\n <BYAPR12MB328611A5DC429DD09244B590CF789@BYAPR12MB3286.namprd12.prod.outlook.com>", "X-MS-Exchange-Transport-Forked": "True", "X-MS-Oob-TLC-OOBClassifiers": "OLM:6790;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n eW3enlOs+fBeTR5gtpbTAxnyfgTUzvVxPzLhs+jkUFjtaxOsvgKWov2G0vioyX+Uhu5/l2lhHfEQarb1iYKO/yGuudno3D2Mh0nj/sfEnEuWAQMV+sdFRxSyBNJLka4EUzkmwH6XMURZZvSE6BAThrvrVnLlLlxkRdE0WzxrYJk9SQbGYKqVCEbMegGlCb2tIeYb4XU1Cc0kdUElR7WtYpZOF8nryZxFuK+SV8Vn9AmI9xMNwVYrHOfBNECQk+MZNMuDXTcvVWXkRpLsDBAeCOEETUTvalNyDsw17fvZZOJ6v2pfWVVDyRS797j78yjqFy7osT1Apb2WahKKbeu/5JzliiPwEptZRfeO+XxbdG6ad5mSM5Z5pT4m6v8Abpeh+6h2tRm2XP0Z2BRQtWaVF/eS+9PB80tAEGS7KgWPl4Rki4RPNV/bbEz9HfF9Kf6uiRk5NCXkC5haxGwLqWm7b0WJdXCusuek1YZL4sh8isvBXOyGATH9TnF7fTP5qbp+L16x2s2JmgwNSjesKlTx13hrGEYrFocmfLz0NuUKJ+KC3zzsUPoUPfsPrrEfdAo/T8+tD9G73mOM2sKnb3z+8ZsY5gCrtXSfhXBCt6/tcaZQ5LebSRb9RSxxzDPGzuPGP5rxv4eNkQoOSJ+QlxgCKlzK1yZy8gevEO58FUtLCn0=", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(346002)(136003)(39860400002)(396003)(376002)(36840700001)(46966006)(6666004)(82310400003)(5660300002)(8676002)(6286002)(36756003)(426003)(8936002)(47076005)(55016002)(2616005)(16526019)(336012)(86362001)(7636003)(186003)(54906003)(70586007)(70206006)(15650500001)(110136005)(82740400003)(356005)(36906005)(316002)(36860700001)(4326008)(7696005)(478600001)(2906002)(83380400001)(1076003)(26005);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "04 Apr 2021 07:46:16.9082 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n f0a2234f-79af-4c25-fb9c-08d8f73dbab0", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT049.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BYAPR12MB3286", "Subject": "[dpdk-dev] [PATCH v4 2/2] ethdev: update qfi definition", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "qfi field is 8 bits which represent single bit for\nPPP (paging Policy Presence) single bit for RQI\n(Reflective QoS Indicator) and 6 bits for qfi\n(QoS Flow Identifier) based on RFC 38415-g30\n\nThis update the doxygen format and the mask for qfi\nto properly identify the full 8 bits of the field.\n\nnote: changing the default mask would cause different\npatterns generated by testpmd.\n\nFixes: 346553db5bd1 (\"ethdev: add GTP extension header to flow API\")\nCc: ying.a.wang@intel.com\nCc: stable@dpdk.org\n\nSigned-off-by: Raslan Darawsheh <rasland@nvidia.com>\n---\n doc/guides/testpmd_app_ug/testpmd_funcs.rst | 3 ++-\n lib/librte_ethdev/rte_flow.h | 20 +++++++++++++++++---\n 2 files changed, 19 insertions(+), 4 deletions(-)", "diff": "diff --git a/doc/guides/testpmd_app_ug/testpmd_funcs.rst b/doc/guides/testpmd_app_ug/testpmd_funcs.rst\nindex f59eb8a27d..dd39c4c3c2 100644\n--- a/doc/guides/testpmd_app_ug/testpmd_funcs.rst\n+++ b/doc/guides/testpmd_app_ug/testpmd_funcs.rst\n@@ -3742,7 +3742,8 @@ This section lists supported pattern items and their attributes, if any.\n - ``gtp_psc``: match GTP PDU extension header with type 0x85.\n \n - ``pdu_type {unsigned}``: PDU type.\n- - ``qfi {unsigned}``: QoS flow identifier.\n+\n+ - ``qfi {unsigned}``: PPP, RQI and QoS flow identifier.\n \n - ``pppoes``, ``pppoed``: match PPPoE header.\n \ndiff --git a/lib/librte_ethdev/rte_flow.h b/lib/librte_ethdev/rte_flow.h\nindex 6cc57136ac..20b4389429 100644\n--- a/lib/librte_ethdev/rte_flow.h\n+++ b/lib/librte_ethdev/rte_flow.h\n@@ -20,6 +20,7 @@\n #include <rte_arp.h>\n #include <rte_common.h>\n #include <rte_ether.h>\n+#include <rte_gtp.h>\n #include <rte_icmp.h>\n #include <rte_ip.h>\n #include <rte_sctp.h>\n@@ -1421,16 +1422,29 @@ static const struct rte_flow_item_meta rte_flow_item_meta_mask = {\n *\n * Matches a GTP PDU extension header with type 0x85.\n */\n+RTE_STD_C11\n struct rte_flow_item_gtp_psc {\n-\tuint8_t pdu_type; /**< PDU type. */\n-\tuint8_t qfi; /**< QoS flow identifier. */\n+\tunion {\n+\t\tstruct {\n+\t\t\t/*\n+\t\t\t * These fields are retained for compatibility.\n+\t\t\t * Please switch to the new header field below.\n+\t\t\t */\n+\t\t\tuint8_t pdu_type; /**< PDU type. */\n+\t\t\tuint8_t qfi; /**< PPP, RQI, QoS flow identifier. */\n+\n+\t\t};\n+\t\tstruct rte_gtp_psc_hdr hdr;\n+\t};\n };\n \n /** Default mask for RTE_FLOW_ITEM_TYPE_GTP_PSC. */\n #ifndef __cplusplus\n static const struct rte_flow_item_gtp_psc\n rte_flow_item_gtp_psc_mask = {\n-\t.qfi = 0x3f,\n+\t.hdr.ppp = 1,\n+\t.hdr.rqi = 1,\n+\t.hdr.qfi = 0x3f,\n };\n #endif\n \n", "prefixes": [ "v4", "2/2" ] }