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GET /api/patches/90423/?format=api
{ "id": 90423, "url": "http://patches.dpdk.org/api/patches/90423/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210401123817.14348-51-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210401123817.14348-51-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210401123817.14348-51-ndabilpuram@marvell.com", "date": "2021-04-01T12:38:15", "name": "[v3,50/52] common/cnxk: add base tim device support", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "a302ef53dd0c334d9fdb4fec722d95f296d89ce1", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210401123817.14348-51-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 16059, "url": "http://patches.dpdk.org/api/series/16059/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=16059", "date": "2021-04-01T12:37:25", "name": "Add Marvell CNXK common driver", "version": 3, "mbox": "http://patches.dpdk.org/series/16059/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/90423/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/90423/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 18871A0548;\n\tThu, 1 Apr 2021 14:45:57 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3B05C1412F0;\n\tThu, 1 Apr 2021 14:41:10 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 13B081412FD\n for <dev@dpdk.org>; Thu, 1 Apr 2021 14:41:07 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 131CQnTk001166 for <dev@dpdk.org>; Thu, 1 Apr 2021 05:41:07 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 37n28j2dy8-3\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 01 Apr 2021 05:41:07 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Thu, 1 Apr 2021 05:41:05 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Thu, 1 Apr 2021 05:41:05 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id EFE213F7040;\n Thu, 1 Apr 2021 05:41:02 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=GUQAnNSVY4HrEJNgolnMkXlNkqxmbCuPruXJZ5s0R1c=;\n b=HbphbM+KlN5ZTCzLyyhYlJNk41tz9hpBtgXnT4ynUiFNl0VqqxZqGr/AOyVRr+IG+jJ2\n w0ivqd67AuKl8spqTa+yBgBzt7yKd7Ac2EY2hhofrGBDufiDXmy4//75ETU68yI0F9pO\n Br63Tbf5n8RdKXKQfYZoPmiGDu9qwuWMkL3+UpAjQFLPJWG0byEH5fuyfrNdmG4rcRMk\n NER4Bp0x8MHS32aynjdiXCX6v2nk/i59WUSxddcROjvFtOMGtn4SUqDK6CYMLyyP/RV7\n iZfZb9LinZ+0Trk5zzZC/gVrV+5wctPPDEpx58eohKTEyj27DXB4XnhQJHuv10BWOHi0 Qg==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>", "Date": "Thu, 1 Apr 2021 18:08:15 +0530", "Message-ID": "<20210401123817.14348-51-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210401123817.14348-1-ndabilpuram@marvell.com>", "References": "<20210305133918.8005-1-ndabilpuram@marvell.com>\n <20210401123817.14348-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "lBg8LbjysEH3YP2z5io1kfXzqIsI95nl", "X-Proofpoint-GUID": "lBg8LbjysEH3YP2z5io1kfXzqIsI95nl", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-04-01_05:2021-03-31,\n 2021-04-01 signatures=0", "Subject": "[dpdk-dev] [PATCH v3 50/52] common/cnxk: add base tim device support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd TIM device init, fini which are used to attach TIM LF\nresources to the RVU PF/VF and TIM LF alloc and free.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/common/cnxk/meson.build | 1 +\n drivers/common/cnxk/roc_api.h | 3 +\n drivers/common/cnxk/roc_platform.c | 1 +\n drivers/common/cnxk/roc_platform.h | 2 +\n drivers/common/cnxk/roc_priv.h | 3 +\n drivers/common/cnxk/roc_tim.c | 263 +++++++++++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_tim.h | 43 ++++++\n drivers/common/cnxk/roc_tim_priv.h | 21 +++\n drivers/common/cnxk/version.map | 9 ++\n 9 files changed, 346 insertions(+)\n create mode 100644 drivers/common/cnxk/roc_tim.c\n create mode 100644 drivers/common/cnxk/roc_tim.h\n create mode 100644 drivers/common/cnxk/roc_tim_priv.h", "diff": "diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build\nindex e6e2ad3..1b02178 100644\n--- a/drivers/common/cnxk/meson.build\n+++ b/drivers/common/cnxk/meson.build\n@@ -42,5 +42,6 @@ sources = files('roc_dev.c',\n \t\t'roc_sso.c',\n \t\t'roc_sso_debug.c',\n \t\t'roc_sso_irq.c',\n+\t\t'roc_tim.c',\n \t\t'roc_utils.c')\n includes += include_directories('../../bus/pci')\ndiff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h\nindex b7fc3b7..67f5d13 100644\n--- a/drivers/common/cnxk/roc_api.h\n+++ b/drivers/common/cnxk/roc_api.h\n@@ -91,6 +91,9 @@\n /* SSO */\n #include \"roc_sso.h\"\n \n+/* TIM */\n+#include \"roc_tim.h\"\n+\n /* Utils */\n #include \"roc_utils.h\"\n \ndiff --git a/drivers/common/cnxk/roc_platform.c b/drivers/common/cnxk/roc_platform.c\nindex 408fe3d..28598cf 100644\n--- a/drivers/common/cnxk/roc_platform.c\n+++ b/drivers/common/cnxk/roc_platform.c\n@@ -34,4 +34,5 @@ RTE_LOG_REGISTER(cnxk_logtype_npa, pmd.mempool.cnxk, NOTICE);\n RTE_LOG_REGISTER(cnxk_logtype_nix, pmd.net.cnxk, NOTICE);\n RTE_LOG_REGISTER(cnxk_logtype_npc, pmd.net.cnxk.flow, NOTICE);\n RTE_LOG_REGISTER(cnxk_logtype_sso, pmd.event.cnxk, NOTICE);\n+RTE_LOG_REGISTER(cnxk_logtype_tim, pmd.event.cnxk.timer, NOTICE);\n RTE_LOG_REGISTER(cnxk_logtype_tm, pmd.net.cnxk.tm, NOTICE);\ndiff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h\nindex 9ea7b1a..c886dc5 100644\n--- a/drivers/common/cnxk/roc_platform.h\n+++ b/drivers/common/cnxk/roc_platform.h\n@@ -138,6 +138,7 @@ extern int cnxk_logtype_npa;\n extern int cnxk_logtype_nix;\n extern int cnxk_logtype_npc;\n extern int cnxk_logtype_sso;\n+extern int cnxk_logtype_tim;\n extern int cnxk_logtype_tm;\n \n #define plt_err(fmt, args...) \\\n@@ -160,6 +161,7 @@ extern int cnxk_logtype_tm;\n #define plt_nix_dbg(fmt, ...)\tplt_dbg(nix, fmt, ##__VA_ARGS__)\n #define plt_npc_dbg(fmt, ...)\tplt_dbg(npc, fmt, ##__VA_ARGS__)\n #define plt_sso_dbg(fmt, ...)\tplt_dbg(sso, fmt, ##__VA_ARGS__)\n+#define plt_tim_dbg(fmt, ...)\tplt_dbg(tim, fmt, ##__VA_ARGS__)\n #define plt_tm_dbg(fmt, ...)\tplt_dbg(tm, fmt, ##__VA_ARGS__)\n \n #ifdef __cplusplus\ndiff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h\nindex dd9d87a..5e7564c 100644\n--- a/drivers/common/cnxk/roc_priv.h\n+++ b/drivers/common/cnxk/roc_priv.h\n@@ -29,4 +29,7 @@\n /* SSO */\n #include \"roc_sso_priv.h\"\n \n+/* TIM */\n+#include \"roc_tim_priv.h\"\n+\n #endif /* _ROC_PRIV_H_ */\ndiff --git a/drivers/common/cnxk/roc_tim.c b/drivers/common/cnxk/roc_tim.c\nnew file mode 100644\nindex 0000000..37faa37\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_tim.c\n@@ -0,0 +1,263 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"roc_api.h\"\n+#include \"roc_priv.h\"\n+\n+static void\n+tim_err_desc(int rc)\n+{\n+\tswitch (rc) {\n+\tcase TIM_AF_NO_RINGS_LEFT:\n+\t\tplt_err(\"Unable to allocate new TIM ring.\");\n+\t\tbreak;\n+\tcase TIM_AF_INVALID_NPA_PF_FUNC:\n+\t\tplt_err(\"Invalid NPA pf func.\");\n+\t\tbreak;\n+\tcase TIM_AF_INVALID_SSO_PF_FUNC:\n+\t\tplt_err(\"Invalid SSO pf func.\");\n+\t\tbreak;\n+\tcase TIM_AF_RING_STILL_RUNNING:\n+\t\tplt_err(\"Ring busy.\");\n+\t\tbreak;\n+\tcase TIM_AF_LF_INVALID:\n+\t\tplt_err(\"Invalid Ring id.\");\n+\t\tbreak;\n+\tcase TIM_AF_CSIZE_NOT_ALIGNED:\n+\t\tplt_err(\"Chunk size specified needs to be multiple of 16.\");\n+\t\tbreak;\n+\tcase TIM_AF_CSIZE_TOO_SMALL:\n+\t\tplt_err(\"Chunk size too small.\");\n+\t\tbreak;\n+\tcase TIM_AF_CSIZE_TOO_BIG:\n+\t\tplt_err(\"Chunk size too big.\");\n+\t\tbreak;\n+\tcase TIM_AF_INTERVAL_TOO_SMALL:\n+\t\tplt_err(\"Bucket traversal interval too small.\");\n+\t\tbreak;\n+\tcase TIM_AF_INVALID_BIG_ENDIAN_VALUE:\n+\t\tplt_err(\"Invalid Big endian value.\");\n+\t\tbreak;\n+\tcase TIM_AF_INVALID_CLOCK_SOURCE:\n+\t\tplt_err(\"Invalid Clock source specified.\");\n+\t\tbreak;\n+\tcase TIM_AF_GPIO_CLK_SRC_NOT_ENABLED:\n+\t\tplt_err(\"GPIO clock source not enabled.\");\n+\t\tbreak;\n+\tcase TIM_AF_INVALID_BSIZE:\n+\t\tplt_err(\"Invalid bucket size.\");\n+\t\tbreak;\n+\tcase TIM_AF_INVALID_ENABLE_PERIODIC:\n+\t\tplt_err(\"Invalid bucket size.\");\n+\t\tbreak;\n+\tcase TIM_AF_INVALID_ENABLE_DONTFREE:\n+\t\tplt_err(\"Invalid Don't free value.\");\n+\t\tbreak;\n+\tcase TIM_AF_ENA_DONTFRE_NSET_PERIODIC:\n+\t\tplt_err(\"Don't free bit not set when periodic is enabled.\");\n+\t\tbreak;\n+\tcase TIM_AF_RING_ALREADY_DISABLED:\n+\t\tplt_err(\"Ring already stopped\");\n+\t\tbreak;\n+\tdefault:\n+\t\tplt_err(\"Unknown Error.\");\n+\t}\n+}\n+\n+int\n+roc_tim_lf_enable(struct roc_tim *roc_tim, uint8_t ring_id, uint64_t *start_tsc,\n+\t\t uint32_t *cur_bkt)\n+{\n+\tstruct dev *dev = &roc_sso_to_sso_priv(roc_tim->roc_sso)->dev;\n+\tstruct tim_enable_rsp *rsp;\n+\tstruct tim_ring_req *req;\n+\tint rc = -ENOSPC;\n+\n+\treq = mbox_alloc_msg_tim_enable_ring(dev->mbox);\n+\tif (req == NULL)\n+\t\treturn rc;\n+\treq->ring = ring_id;\n+\n+\trc = mbox_process_msg(dev->mbox, (void **)&rsp);\n+\tif (rc < 0) {\n+\t\ttim_err_desc(rc);\n+\t\treturn rc;\n+\t}\n+\n+\tif (cur_bkt)\n+\t\t*cur_bkt = rsp->currentbucket;\n+\tif (start_tsc)\n+\t\t*start_tsc = rsp->timestarted;\n+\n+\treturn 0;\n+}\n+\n+int\n+roc_tim_lf_disable(struct roc_tim *roc_tim, uint8_t ring_id)\n+{\n+\tstruct dev *dev = &roc_sso_to_sso_priv(roc_tim->roc_sso)->dev;\n+\tstruct tim_ring_req *req;\n+\tint rc = -ENOSPC;\n+\n+\treq = mbox_alloc_msg_tim_disable_ring(dev->mbox);\n+\tif (req == NULL)\n+\t\treturn rc;\n+\treq->ring = ring_id;\n+\n+\trc = mbox_process(dev->mbox);\n+\tif (rc < 0) {\n+\t\ttim_err_desc(rc);\n+\t\treturn rc;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+uintptr_t\n+roc_tim_lf_base_get(struct roc_tim *roc_tim, uint8_t ring_id)\n+{\n+\tstruct dev *dev = &roc_sso_to_sso_priv(roc_tim->roc_sso)->dev;\n+\n+\treturn dev->bar2 + (RVU_BLOCK_ADDR_TIM << 20 | ring_id << 12);\n+}\n+\n+int\n+roc_tim_lf_config(struct roc_tim *roc_tim, uint8_t ring_id,\n+\t\t enum roc_tim_clk_src clk_src, uint8_t ena_periodic,\n+\t\t uint8_t ena_dfb, uint32_t bucket_sz, uint32_t chunk_sz,\n+\t\t uint32_t interval)\n+{\n+\tstruct dev *dev = &roc_sso_to_sso_priv(roc_tim->roc_sso)->dev;\n+\tstruct tim_config_req *req;\n+\tint rc = -ENOSPC;\n+\n+\treq = mbox_alloc_msg_tim_config_ring(dev->mbox);\n+\tif (req == NULL)\n+\t\treturn rc;\n+\treq->ring = ring_id;\n+\treq->bigendian = false;\n+\treq->bucketsize = bucket_sz;\n+\treq->chunksize = chunk_sz;\n+\treq->clocksource = clk_src;\n+\treq->enableperiodic = ena_periodic;\n+\treq->enabledontfreebuffer = ena_dfb;\n+\treq->interval = interval;\n+\treq->gpioedge = TIM_GPIO_LTOH_TRANS;\n+\n+\trc = mbox_process(dev->mbox);\n+\tif (rc < 0) {\n+\t\ttim_err_desc(rc);\n+\t\treturn rc;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int\n+roc_tim_lf_alloc(struct roc_tim *roc_tim, uint8_t ring_id, uint64_t *clk)\n+{\n+\tstruct sso *sso = roc_sso_to_sso_priv(roc_tim->roc_sso);\n+\tstruct tim_lf_alloc_req *req;\n+\tstruct tim_lf_alloc_rsp *rsp;\n+\tstruct dev *dev = &sso->dev;\n+\tint rc = -ENOSPC;\n+\n+\treq = mbox_alloc_msg_tim_lf_alloc(dev->mbox);\n+\tif (req == NULL)\n+\t\treturn rc;\n+\treq->npa_pf_func = idev_npa_pffunc_get();\n+\treq->sso_pf_func = idev_sso_pffunc_get();\n+\treq->ring = ring_id;\n+\n+\trc = mbox_process_msg(dev->mbox, (void **)&rsp);\n+\tif (rc < 0) {\n+\t\ttim_err_desc(rc);\n+\t\treturn rc;\n+\t}\n+\n+\tif (clk)\n+\t\t*clk = rsp->tenns_clk;\n+\n+\treturn rc;\n+}\n+\n+int\n+roc_tim_lf_free(struct roc_tim *roc_tim, uint8_t ring_id)\n+{\n+\tstruct sso *sso = roc_sso_to_sso_priv(roc_tim->roc_sso);\n+\tstruct dev *dev = &sso->dev;\n+\tstruct tim_ring_req *req;\n+\tint rc = -ENOSPC;\n+\n+\treq = mbox_alloc_msg_tim_lf_free(dev->mbox);\n+\tif (req == NULL)\n+\t\treturn rc;\n+\treq->ring = ring_id;\n+\n+\trc = mbox_process(dev->mbox);\n+\tif (rc < 0) {\n+\t\ttim_err_desc(rc);\n+\t\treturn rc;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int\n+roc_tim_init(struct roc_tim *roc_tim)\n+{\n+\tstruct rsrc_attach_req *attach_req;\n+\tstruct free_rsrcs_rsp *free_rsrc;\n+\tstruct dev *dev;\n+\tuint16_t nb_lfs;\n+\tint rc;\n+\n+\tif (roc_tim == NULL || roc_tim->roc_sso == NULL)\n+\t\treturn TIM_ERR_PARAM;\n+\n+\tPLT_STATIC_ASSERT(sizeof(struct tim) <= TIM_MEM_SZ);\n+\tdev = &roc_sso_to_sso_priv(roc_tim->roc_sso)->dev;\n+\tnb_lfs = roc_tim->nb_lfs;\n+\tmbox_alloc_msg_free_rsrc_cnt(dev->mbox);\n+\trc = mbox_process_msg(dev->mbox, (void *)&free_rsrc);\n+\tif (rc < 0) {\n+\t\tplt_err(\"Unable to get free rsrc count.\");\n+\t\treturn 0;\n+\t}\n+\n+\tif (nb_lfs && (free_rsrc->tim < nb_lfs)) {\n+\t\tplt_tim_dbg(\"Requested LFs : %d Available LFs : %d\", nb_lfs,\n+\t\t\t free_rsrc->tim);\n+\t\treturn 0;\n+\t}\n+\n+\tattach_req = mbox_alloc_msg_attach_resources(dev->mbox);\n+\tif (attach_req == NULL)\n+\t\treturn -ENOSPC;\n+\tattach_req->modify = true;\n+\tattach_req->timlfs = nb_lfs ? nb_lfs : free_rsrc->tim;\n+\tnb_lfs = attach_req->timlfs;\n+\n+\trc = mbox_process(dev->mbox);\n+\tif (rc < 0) {\n+\t\tplt_err(\"Unable to attach TIM LFs.\");\n+\t\treturn 0;\n+\t}\n+\n+\treturn nb_lfs;\n+}\n+\n+void\n+roc_tim_fini(struct roc_tim *roc_tim)\n+{\n+\tstruct dev *dev = &roc_sso_to_sso_priv(roc_tim->roc_sso)->dev;\n+\tstruct rsrc_detach_req *detach_req;\n+\n+\tdetach_req = mbox_alloc_msg_detach_resources(dev->mbox);\n+\tPLT_ASSERT(detach_req);\n+\tdetach_req->partial = true;\n+\tdetach_req->timlfs = true;\n+\n+\tmbox_process(dev->mbox);\n+}\ndiff --git a/drivers/common/cnxk/roc_tim.h b/drivers/common/cnxk/roc_tim.h\nnew file mode 100644\nindex 0000000..159b021\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_tim.h\n@@ -0,0 +1,43 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#ifndef _ROC_TIM_H_\n+#define _ROC_TIM_H_\n+\n+enum roc_tim_clk_src {\n+\tROC_TIM_CLK_SRC_10NS = 0,\n+\tROC_TIM_CLK_SRC_GPIO,\n+\tROC_TIM_CLK_SRC_GTI,\n+\tROC_TIM_CLK_SRC_PTP,\n+\tROC_TIM_CLK_SRC_INVALID,\n+};\n+\n+struct roc_tim {\n+\tstruct roc_sso *roc_sso;\n+\t/* Public data. */\n+\tuint16_t nb_lfs;\n+\t/* Private data. */\n+#define TIM_MEM_SZ (1 * 1024)\n+\tuint8_t reserved[TIM_MEM_SZ] __plt_cache_aligned;\n+} __plt_cache_aligned;\n+\n+int __roc_api roc_tim_init(struct roc_tim *roc_tim);\n+void __roc_api roc_tim_fini(struct roc_tim *roc_tim);\n+\n+/* TIM config */\n+int __roc_api roc_tim_lf_enable(struct roc_tim *roc_tim, uint8_t ring_id,\n+\t\t\t\tuint64_t *start_tsc, uint32_t *cur_bkt);\n+int __roc_api roc_tim_lf_disable(struct roc_tim *roc_tim, uint8_t ring_id);\n+int __roc_api roc_tim_lf_config(struct roc_tim *roc_tim, uint8_t ring_id,\n+\t\t\t\tenum roc_tim_clk_src clk_src,\n+\t\t\t\tuint8_t ena_periodic, uint8_t ena_dfb,\n+\t\t\t\tuint32_t bucket_sz, uint32_t chunk_sz,\n+\t\t\t\tuint32_t interval);\n+int __roc_api roc_tim_lf_alloc(struct roc_tim *roc_tim, uint8_t ring_id,\n+\t\t\t uint64_t *clk);\n+int __roc_api roc_tim_lf_free(struct roc_tim *roc_tim, uint8_t ring_id);\n+uintptr_t __roc_api roc_tim_lf_base_get(struct roc_tim *roc_tim,\n+\t\t\t\t\tuint8_t ring_id);\n+\n+#endif\ndiff --git a/drivers/common/cnxk/roc_tim_priv.h b/drivers/common/cnxk/roc_tim_priv.h\nnew file mode 100644\nindex 0000000..08697f6\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_tim_priv.h\n@@ -0,0 +1,21 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#ifndef _ROC_TIM_PRIV_H_\n+#define _ROC_TIM_PRIV_H_\n+\n+struct tim {\n+};\n+\n+enum tim_err_status {\n+\tTIM_ERR_PARAM = -5120,\n+};\n+\n+static inline struct tim *\n+roc_tim_to_tim_priv(struct roc_tim *roc_tim)\n+{\n+\treturn (struct tim *)&roc_tim->reserved[0];\n+}\n+\n+#endif /* _ROC_TIM_PRIV_H_ */\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex e93d623..9b3c5a0 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -7,6 +7,7 @@ INTERNAL {\n \tcnxk_logtype_npa;\n \tcnxk_logtype_npc;\n \tcnxk_logtype_sso;\n+\tcnxk_logtype_tim;\n \tcnxk_logtype_tm;\n \troc_clk_freq_get;\n \troc_error_msg_get;\n@@ -189,6 +190,14 @@ INTERNAL {\n \troc_sso_ns_to_gw;\n \troc_sso_rsrc_fini;\n \troc_sso_rsrc_init;\n+\troc_tim_fini;\n+\troc_tim_init;\n+\troc_tim_lf_alloc;\n+\troc_tim_lf_base_get;\n+\troc_tim_lf_config;\n+\troc_tim_lf_disable;\n+\troc_tim_lf_enable;\n+\troc_tim_lf_free;\n \n \tlocal: *;\n };\n", "prefixes": [ "v3", "50/52" ] }