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GET /api/patches/90188/?format=api
{ "id": 90188, "url": "http://patches.dpdk.org/api/patches/90188/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210331073749.1382377-5-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210331073749.1382377-5-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210331073749.1382377-5-suanmingm@nvidia.com", "date": "2021-03-31T07:37:49", "name": "[v4,4/4] regex/mlx5: prevent wrong calculation of free sqs in umr mode", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "f2bacadc38c1f732c844689561a498d470ab4d07", "submitter": { "id": 1887, "url": "http://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210331073749.1382377-5-suanmingm@nvidia.com/mbox/", "series": [ { "id": 15999, "url": "http://patches.dpdk.org/api/series/15999/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=15999", "date": "2021-03-31T07:37:45", "name": "regex/mlx5: support scattered mbuf", "version": 4, "mbox": "http://patches.dpdk.org/series/15999/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/90188/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/90188/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 9D12AA034F;\n\tWed, 31 Mar 2021 09:38:56 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id C2383140E32;\n\tWed, 31 Mar 2021 09:38:06 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by mails.dpdk.org (Postfix) with ESMTP id 749D5140E12\n for <dev@dpdk.org>; Wed, 31 Mar 2021 09:38:00 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n suanmingm@nvidia.com) with SMTP; 31 Mar 2021 10:37:59 +0300", "from nvidia.com (mtbc-r640-03.mtbc.labs.mlnx [10.75.70.8])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 12V7boeI002108;\n Wed, 31 Mar 2021 10:37:57 +0300" ], "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "orika@nvidia.com", "Cc": "dev@dpdk.org, viacheslavo@nvidia.com, matan@nvidia.com,\n rasland@nvidia.com,\n John Hurley <jhurley@nvidia.com>", "Date": "Wed, 31 Mar 2021 10:37:49 +0300", "Message-Id": "<20210331073749.1382377-5-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210331073749.1382377-1-suanmingm@nvidia.com>", "References": "<20210309235732.3952418-1-suanmingm@nvidia.com>\n <20210331073749.1382377-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v4 4/4] regex/mlx5: prevent wrong calculation of\n free sqs in umr mode", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: John Hurley <jhurley@nvidia.com>\n\nA recent change adds support for scattered mbuf and UMR support for regex.\nPart of this commit makes the pi and ci counters of the regex_sq a quarter\nof the length in non umr mode, effectively moving them from 16 bits to\n14. The new get_free method casts the difference in pi and ci to a 16 bit\nvalue when calculating the free send queues, accounting for any wrapping\nwhen pi has looped back to 0 but ci has not yet. However, the move to 14\nbits while still casting to 16 can now lead to corrupted, large values\nreturned.\n\nModify the get_free function to take in the has_umr flag and, accordingly,\naccount for wrapping on either 14 or 16 bit pi/ci difference.\n\nFixes: 017f097021a6 (\"regex/mlx5: add data path scattered mbuf process\")\nSigned-off-by: John Hurley <jhurley@nvidia.com>\nAcked-by: Ori Kam <orika@nvidia.com>\n---\n drivers/regex/mlx5/mlx5_regex_fastpath.c | 10 ++++++----\n 1 file changed, 6 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/regex/mlx5/mlx5_regex_fastpath.c b/drivers/regex/mlx5/mlx5_regex_fastpath.c\nindex 4f9402c583..b57e7d7794 100644\n--- a/drivers/regex/mlx5/mlx5_regex_fastpath.c\n+++ b/drivers/regex/mlx5/mlx5_regex_fastpath.c\n@@ -192,8 +192,10 @@ send_doorbell(struct mlx5_regex_priv *priv, struct mlx5_regex_sq *sq)\n }\n \n static inline int\n-get_free(struct mlx5_regex_sq *sq) {\n-\treturn (sq_size_get(sq) - (uint16_t)(sq->pi - sq->ci));\n+get_free(struct mlx5_regex_sq *sq, uint8_t has_umr) {\n+\treturn (sq_size_get(sq) - ((sq->pi - sq->ci) &\n+\t\t\t(has_umr ? (MLX5_REGEX_MAX_WQE_INDEX >> 2) :\n+\t\t\tMLX5_REGEX_MAX_WQE_INDEX)));\n }\n \n static inline uint32_t\n@@ -385,7 +387,7 @@ mlx5_regexdev_enqueue_gga(struct rte_regexdev *dev, uint16_t qp_id,\n \twhile ((sqid = ffs(queue->free_sqs))) {\n \t\tsqid--; /* ffs returns 1 for bit 0 */\n \t\tsq = &queue->sqs[sqid];\n-\t\tnb_desc = get_free(sq);\n+\t\tnb_desc = get_free(sq, priv->has_umr);\n \t\tif (nb_desc) {\n \t\t\t/* The ops be handled can't exceed nb_ops. */\n \t\t\tif (nb_desc > nb_left)\n@@ -418,7 +420,7 @@ mlx5_regexdev_enqueue(struct rte_regexdev *dev, uint16_t qp_id,\n \twhile ((sqid = ffs(queue->free_sqs))) {\n \t\tsqid--; /* ffs returns 1 for bit 0 */\n \t\tsq = &queue->sqs[sqid];\n-\t\twhile (get_free(sq)) {\n+\t\twhile (get_free(sq, priv->has_umr)) {\n \t\t\tjob_id = job_id_get(sqid, sq_size_get(sq), sq->pi);\n \t\t\tprep_one(priv, queue, sq, ops[i], &queue->jobs[job_id]);\n \t\t\ti++;\n", "prefixes": [ "v4", "4/4" ] }