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GET /api/patches/89297/?format=api
{ "id": 89297, "url": "http://patches.dpdk.org/api/patches/89297/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210316221857.2254-20-timothy.mcdaniel@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210316221857.2254-20-timothy.mcdaniel@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210316221857.2254-20-timothy.mcdaniel@intel.com", "date": "2021-03-16T22:18:51", "name": "[19/25] event/dlb2: delete old dlb2_resource.c file", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "c6c637faaf203abe5e49200ff08282929c55dd69", "submitter": { "id": 826, "url": "http://patches.dpdk.org/api/people/826/?format=api", "name": "Timothy McDaniel", "email": "timothy.mcdaniel@intel.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210316221857.2254-20-timothy.mcdaniel@intel.com/mbox/", "series": [ { "id": 15709, "url": "http://patches.dpdk.org/api/series/15709/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=15709", "date": "2021-03-16T22:18:32", "name": "Add Support for DLB v2.5", "version": 1, "mbox": "http://patches.dpdk.org/series/15709/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/89297/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/89297/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 89D82A054F;\n\tTue, 16 Mar 2021 23:22:13 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 420AA242B0B;\n\tTue, 16 Mar 2021 23:20:23 +0100 (CET)", "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n by mails.dpdk.org (Postfix) with ESMTP id 3791C242AA3\n for <dev@dpdk.org>; Tue, 16 Mar 2021 23:20:04 +0100 (CET)", "from fmsmga005.fm.intel.com ([10.253.24.32])\n by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 16 Mar 2021 15:20:02 -0700", "from txasoft-yocto.an.intel.com ([10.123.72.192])\n by fmsmga005.fm.intel.com with ESMTP; 16 Mar 2021 15:20:01 -0700" ], "IronPort-SDR": [ "\n a2zfd8Pz4Zop6dZE6FelMXRcQsmRlnIpl+gAnxiGDTzgsTNSsRBXGdGzcBDQQcf+SVRjPxGUxm\n nsHzfsuXxReA==", "\n y1tbkzwtrREggPXFA71QrcEgRkeEP9JvJOPU01ggY07MGj5cJwM7tEf4afYmSVQx5NQxXjF5wn\n AQSiwwUWruRw==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9925\"; a=\"253359276\"", "E=Sophos;i=\"5.81,254,1610438400\"; d=\"scan'208\";a=\"253359276\"", "E=Sophos;i=\"5.81,254,1610438400\"; d=\"scan'208\";a=\"605440307\"" ], "X-ExtLoop1": "1", "From": "Timothy McDaniel <timothy.mcdaniel@intel.com>", "To": "dev@dpdk.org", "Cc": "jerinj@marvell.com, harry.van.haaren@intel.com, mdr@ashroe.eu,\n nhorman@tuxdriver.com, nikhil.rao@intel.com, erik.g.carrillo@intel.com,\n abhinandan.gujjar@intel.com, pbhagavatula@marvell.com,\n hemant.agrawal@nxp.com, mattias.ronnblom@ericsson.com,\n peter.mccarthy@intel.com", "Date": "Tue, 16 Mar 2021 17:18:51 -0500", "Message-Id": "<20210316221857.2254-20-timothy.mcdaniel@intel.com>", "X-Mailer": "git-send-email 2.23.0", "In-Reply-To": "<20210316221857.2254-1-timothy.mcdaniel@intel.com>", "References": "<20210316221857.2254-1-timothy.mcdaniel@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH 19/25] event/dlb2: delete old dlb2_resource.c file", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The file dlb_resource_new.c now contains all of the low level\nfunctions required to support both DLB v2.0 and DLB v2.5, so\ndelete the temporary \"old\" file, and stop building it. The new\nfile (dlb_resource_new.c) will be renamed to dlb_resource.c in\nthe next commit.\n\nSigned-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>\n---\n drivers/event/dlb2/meson.build | 1 -\n drivers/event/dlb2/pf/base/dlb2_resource.c | 245 ---------------------\n 2 files changed, 246 deletions(-)\n delete mode 100644 drivers/event/dlb2/pf/base/dlb2_resource.c", "diff": "diff --git a/drivers/event/dlb2/meson.build b/drivers/event/dlb2/meson.build\nindex bded07e06..d8cfd377f 100644\n--- a/drivers/event/dlb2/meson.build\n+++ b/drivers/event/dlb2/meson.build\n@@ -13,7 +13,6 @@ sources = files('dlb2.c',\n \t\t'dlb2_xstats.c',\n \t\t'pf/dlb2_main.c',\n \t\t'pf/dlb2_pf.c',\n-\t\t'pf/base/dlb2_resource.c',\n \t\t'pf/base/dlb2_resource_new.c',\n \t\t'rte_pmd_dlb2.c',\n \t\t'dlb2_selftest.c'\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_resource.c b/drivers/event/dlb2/pf/base/dlb2_resource.c\ndeleted file mode 100644\nindex bd1404f33..000000000\n--- a/drivers/event/dlb2/pf/base/dlb2_resource.c\n+++ /dev/null\n@@ -1,245 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2016-2020 Intel Corporation\n- */\n-\n-#include \"dlb2_user.h\"\n-\n-#include \"dlb2_hw_types.h\"\n-#include \"dlb2_mbox.h\"\n-#include \"dlb2_osdep.h\"\n-#include \"dlb2_osdep_bitmap.h\"\n-#include \"dlb2_osdep_types.h\"\n-#include \"dlb2_regs.h\"\n-#include \"dlb2_resource.h\"\n-\n-#include \"../../dlb2_priv.h\"\n-#include \"../../dlb2_inline_fns.h\"\n-\n-#define DLB2_DOM_LIST_HEAD(head, type) \\\n-\tDLB2_LIST_HEAD((head), type, domain_list)\n-\n-#define DLB2_FUNC_LIST_HEAD(head, type) \\\n-\tDLB2_LIST_HEAD((head), type, func_list)\n-\n-#define DLB2_DOM_LIST_FOR(head, ptr, iter) \\\n-\tDLB2_LIST_FOR_EACH(head, ptr, domain_list, iter)\n-\n-#define DLB2_FUNC_LIST_FOR(head, ptr, iter) \\\n-\tDLB2_LIST_FOR_EACH(head, ptr, func_list, iter)\n-\n-#define DLB2_DOM_LIST_FOR_SAFE(head, ptr, ptr_tmp, it, it_tmp) \\\n-\tDLB2_LIST_FOR_EACH_SAFE((head), ptr, ptr_tmp, domain_list, it, it_tmp)\n-\n-#define DLB2_FUNC_LIST_FOR_SAFE(head, ptr, ptr_tmp, it, it_tmp) \\\n-\tDLB2_LIST_FOR_EACH_SAFE((head), ptr, ptr_tmp, func_list, it, it_tmp)\n-\n-/*\n- * The PF driver cannot assume that a register write will affect subsequent HCW\n- * writes. To ensure a write completes, the driver must read back a CSR. This\n- * function only need be called for configuration that can occur after the\n- * domain has started; prior to starting, applications can't send HCWs.\n- */\n-static inline void dlb2_flush_csr(struct dlb2_hw *hw)\n-{\n-\tDLB2_CSR_RD(hw, DLB2_SYS_TOTAL_VAS);\n-}\n-\n-int dlb2_get_group_sequence_numbers(struct dlb2_hw *hw, unsigned int group_id)\n-{\n-\tif (group_id >= DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS)\n-\t\treturn -EINVAL;\n-\n-\treturn hw->rsrcs.sn_groups[group_id].sequence_numbers_per_queue;\n-}\n-\n-int dlb2_get_group_sequence_number_occupancy(struct dlb2_hw *hw,\n-\t\t\t\t\t unsigned int group_id)\n-{\n-\tif (group_id >= DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS)\n-\t\treturn -EINVAL;\n-\n-\treturn dlb2_sn_group_used_slots(&hw->rsrcs.sn_groups[group_id]);\n-}\n-\n-static void dlb2_log_set_group_sequence_numbers(struct dlb2_hw *hw,\n-\t\t\t\t\t\tunsigned int group_id,\n-\t\t\t\t\t\tunsigned long val)\n-{\n-\tDLB2_HW_DBG(hw, \"DLB2 set group sequence numbers:\\n\");\n-\tDLB2_HW_DBG(hw, \"\\tGroup ID: %u\\n\", group_id);\n-\tDLB2_HW_DBG(hw, \"\\tValue: %lu\\n\", val);\n-}\n-\n-int dlb2_set_group_sequence_numbers(struct dlb2_hw *hw,\n-\t\t\t\t unsigned int group_id,\n-\t\t\t\t unsigned long val)\n-{\n-\tu32 valid_allocations[] = {64, 128, 256, 512, 1024};\n-\tunion dlb2_ro_pipe_grp_sn_mode r0 = { {0} };\n-\tstruct dlb2_sn_group *group;\n-\tint mode;\n-\n-\tif (group_id >= DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS)\n-\t\treturn -EINVAL;\n-\n-\tgroup = &hw->rsrcs.sn_groups[group_id];\n-\n-\t/*\n-\t * Once the first load-balanced queue using an SN group is configured,\n-\t * the group cannot be changed.\n-\t */\n-\tif (group->slot_use_bitmap != 0)\n-\t\treturn -EPERM;\n-\n-\tfor (mode = 0; mode < DLB2_MAX_NUM_SEQUENCE_NUMBER_MODES; mode++)\n-\t\tif (val == valid_allocations[mode])\n-\t\t\tbreak;\n-\n-\tif (mode == DLB2_MAX_NUM_SEQUENCE_NUMBER_MODES)\n-\t\treturn -EINVAL;\n-\n-\tgroup->mode = mode;\n-\tgroup->sequence_numbers_per_queue = val;\n-\n-\tr0.field.sn_mode_0 = hw->rsrcs.sn_groups[0].mode;\n-\tr0.field.sn_mode_1 = hw->rsrcs.sn_groups[1].mode;\n-\n-\tDLB2_CSR_WR(hw, DLB2_RO_PIPE_GRP_SN_MODE, r0.val);\n-\n-\tdlb2_log_set_group_sequence_numbers(hw, group_id, val);\n-\n-\treturn 0;\n-}\n-\n-static struct dlb2_dir_pq_pair *\n-dlb2_get_domain_used_dir_pq(struct dlb2_hw *hw,\n-\t\t\t u32 id,\n-\t\t\t bool vdev_req,\n-\t\t\t struct dlb2_hw_domain *domain)\n-{\n-\tstruct dlb2_list_entry *iter;\n-\tstruct dlb2_dir_pq_pair *port;\n-\tRTE_SET_USED(iter);\n-\n-\tif (id >= DLB2_MAX_NUM_DIR_PORTS(hw->ver))\n-\t\treturn NULL;\n-\n-\tDLB2_DOM_LIST_FOR(domain->used_dir_pq_pairs, port, iter)\n-\t\tif ((!vdev_req && port->id.phys_id == id) ||\n-\t\t (vdev_req && port->id.virt_id == id))\n-\t\t\treturn port;\n-\n-\treturn NULL;\n-}\n-\n-static struct dlb2_ldb_queue *\n-dlb2_get_domain_ldb_queue(u32 id,\n-\t\t\t bool vdev_req,\n-\t\t\t struct dlb2_hw_domain *domain)\n-{\n-\tstruct dlb2_list_entry *iter;\n-\tstruct dlb2_ldb_queue *queue;\n-\tRTE_SET_USED(iter);\n-\n-\tif (id >= DLB2_MAX_NUM_LDB_QUEUES)\n-\t\treturn NULL;\n-\n-\tDLB2_DOM_LIST_FOR(domain->used_ldb_queues, queue, iter)\n-\t\tif ((!vdev_req && queue->id.phys_id == id) ||\n-\t\t (vdev_req && queue->id.virt_id == id))\n-\t\t\treturn queue;\n-\n-\treturn NULL;\n-}\n-\n-static void dlb2_log_get_dir_queue_depth(struct dlb2_hw *hw,\n-\t\t\t\t\t u32 domain_id,\n-\t\t\t\t\t u32 queue_id,\n-\t\t\t\t\t bool vdev_req,\n-\t\t\t\t\t unsigned int vf_id)\n-{\n-\tDLB2_HW_DBG(hw, \"DLB get directed queue depth:\\n\");\n-\tif (vdev_req)\n-\t\tDLB2_HW_DBG(hw, \"(Request from VF %d)\\n\", vf_id);\n-\tDLB2_HW_DBG(hw, \"\\tDomain ID: %d\\n\", domain_id);\n-\tDLB2_HW_DBG(hw, \"\\tQueue ID: %d\\n\", queue_id);\n-}\n-\n-int dlb2_hw_get_dir_queue_depth(struct dlb2_hw *hw,\n-\t\t\t\tu32 domain_id,\n-\t\t\t\tstruct dlb2_get_dir_queue_depth_args *args,\n-\t\t\t\tstruct dlb2_cmd_response *resp,\n-\t\t\t\tbool vdev_req,\n-\t\t\t\tunsigned int vdev_id)\n-{\n-\tstruct dlb2_dir_pq_pair *queue;\n-\tstruct dlb2_hw_domain *domain;\n-\tint id;\n-\n-\tid = domain_id;\n-\n-\tdlb2_log_get_dir_queue_depth(hw, domain_id, args->queue_id,\n-\t\t\t\t vdev_req, vdev_id);\n-\n-\tdomain = dlb2_get_domain_from_id(hw, id, vdev_req, vdev_id);\n-\tif (domain == NULL) {\n-\t\tresp->status = DLB2_ST_INVALID_DOMAIN_ID;\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tid = args->queue_id;\n-\n-\tqueue = dlb2_get_domain_used_dir_pq(hw, id, vdev_req, domain);\n-\tif (queue == NULL) {\n-\t\tresp->status = DLB2_ST_INVALID_QID;\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tresp->id = dlb2_dir_queue_depth(hw, queue);\n-\n-\treturn 0;\n-}\n-\n-static void dlb2_log_get_ldb_queue_depth(struct dlb2_hw *hw,\n-\t\t\t\t\t u32 domain_id,\n-\t\t\t\t\t u32 queue_id,\n-\t\t\t\t\t bool vdev_req,\n-\t\t\t\t\t unsigned int vf_id)\n-{\n-\tDLB2_HW_DBG(hw, \"DLB get load-balanced queue depth:\\n\");\n-\tif (vdev_req)\n-\t\tDLB2_HW_DBG(hw, \"(Request from VF %d)\\n\", vf_id);\n-\tDLB2_HW_DBG(hw, \"\\tDomain ID: %d\\n\", domain_id);\n-\tDLB2_HW_DBG(hw, \"\\tQueue ID: %d\\n\", queue_id);\n-}\n-\n-int dlb2_hw_get_ldb_queue_depth(struct dlb2_hw *hw,\n-\t\t\t\tu32 domain_id,\n-\t\t\t\tstruct dlb2_get_ldb_queue_depth_args *args,\n-\t\t\t\tstruct dlb2_cmd_response *resp,\n-\t\t\t\tbool vdev_req,\n-\t\t\t\tunsigned int vdev_id)\n-{\n-\tstruct dlb2_hw_domain *domain;\n-\tstruct dlb2_ldb_queue *queue;\n-\n-\tdlb2_log_get_ldb_queue_depth(hw, domain_id, args->queue_id,\n-\t\t\t\t vdev_req, vdev_id);\n-\n-\tdomain = dlb2_get_domain_from_id(hw, domain_id, vdev_req, vdev_id);\n-\tif (domain == NULL) {\n-\t\tresp->status = DLB2_ST_INVALID_DOMAIN_ID;\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tqueue = dlb2_get_domain_ldb_queue(args->queue_id, vdev_req, domain);\n-\tif (queue == NULL) {\n-\t\tresp->status = DLB2_ST_INVALID_QID;\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tresp->id = dlb2_ldb_queue_depth(hw, queue);\n-\n-\treturn 0;\n-}\n-\n", "prefixes": [ "19/25" ] }