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GET /api/patches/89293/?format=api
{ "id": 89293, "url": "http://patches.dpdk.org/api/patches/89293/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210316221857.2254-17-timothy.mcdaniel@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210316221857.2254-17-timothy.mcdaniel@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210316221857.2254-17-timothy.mcdaniel@intel.com", "date": "2021-03-16T22:18:48", "name": "[16/25] event/dlb2: add DLB v2.5 sparse cq mode", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "57d1c596e4c9e469006c015e3274cf3f44bfbea2", "submitter": { "id": 826, "url": "http://patches.dpdk.org/api/people/826/?format=api", "name": "Timothy McDaniel", "email": "timothy.mcdaniel@intel.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210316221857.2254-17-timothy.mcdaniel@intel.com/mbox/", "series": [ { "id": 15709, "url": "http://patches.dpdk.org/api/series/15709/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=15709", "date": "2021-03-16T22:18:32", "name": "Add Support for DLB v2.5", "version": 1, "mbox": "http://patches.dpdk.org/series/15709/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/89293/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/89293/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 28951A054F;\n\tTue, 16 Mar 2021 23:21:52 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3CA70242AFC;\n\tTue, 16 Mar 2021 23:20:18 +0100 (CET)", "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n by mails.dpdk.org (Postfix) with ESMTP id 8C719242AA3\n for <dev@dpdk.org>; Tue, 16 Mar 2021 23:20:03 +0100 (CET)", "from fmsmga005.fm.intel.com ([10.253.24.32])\n by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 16 Mar 2021 15:19:59 -0700", "from txasoft-yocto.an.intel.com ([10.123.72.192])\n by fmsmga005.fm.intel.com with ESMTP; 16 Mar 2021 15:19:59 -0700" ], "IronPort-SDR": [ "\n Z6c72Qzg7Ykgbx0odSmlgcc9bxfdPj0pjZiWNM3CyQNBkg93UiqkHK8eaFjroTN6iTMQZuDADa\n xsd476Y9PbcA==", "\n kieZELocdeVDd5UnOPmQGdxuh3LHZjhw4z9q3whKf7oUq17aOG3wGH28v/QbGonmC5ZVLMfdLb\n MBgaC8dhzkww==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9925\"; a=\"253359264\"", "E=Sophos;i=\"5.81,254,1610438400\"; d=\"scan'208\";a=\"253359264\"", "E=Sophos;i=\"5.81,254,1610438400\"; d=\"scan'208\";a=\"605440278\"" ], "X-ExtLoop1": "1", "From": "Timothy McDaniel <timothy.mcdaniel@intel.com>", "To": "dev@dpdk.org", "Cc": "jerinj@marvell.com, harry.van.haaren@intel.com, mdr@ashroe.eu,\n nhorman@tuxdriver.com, nikhil.rao@intel.com, erik.g.carrillo@intel.com,\n abhinandan.gujjar@intel.com, pbhagavatula@marvell.com,\n hemant.agrawal@nxp.com, mattias.ronnblom@ericsson.com,\n peter.mccarthy@intel.com", "Date": "Tue, 16 Mar 2021 17:18:48 -0500", "Message-Id": "<20210316221857.2254-17-timothy.mcdaniel@intel.com>", "X-Mailer": "git-send-email 2.23.0", "In-Reply-To": "<20210316221857.2254-1-timothy.mcdaniel@intel.com>", "References": "<20210316221857.2254-1-timothy.mcdaniel@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH 16/25] event/dlb2: add DLB v2.5 sparse cq mode", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Update sparse cq mode mode functions for DLB v2.5, accounting for new\ncombined register map and hardware access macros.\n\nSigned-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>\n---\n drivers/event/dlb2/pf/base/dlb2_resource.c | 22 -----------\n .../event/dlb2/pf/base/dlb2_resource_new.c | 39 +++++++++++++++++++\n 2 files changed, 39 insertions(+), 22 deletions(-)", "diff": "diff --git a/drivers/event/dlb2/pf/base/dlb2_resource.c b/drivers/event/dlb2/pf/base/dlb2_resource.c\nindex d66442c19..1759cee6b 100644\n--- a/drivers/event/dlb2/pf/base/dlb2_resource.c\n+++ b/drivers/event/dlb2/pf/base/dlb2_resource.c\n@@ -33,28 +33,6 @@\n #define DLB2_FUNC_LIST_FOR_SAFE(head, ptr, ptr_tmp, it, it_tmp) \\\n \tDLB2_LIST_FOR_EACH_SAFE((head), ptr, ptr_tmp, func_list, it, it_tmp)\n \n-void dlb2_hw_enable_sparse_dir_cq_mode(struct dlb2_hw *hw)\n-{\n-\tunion dlb2_chp_cfg_chp_csr_ctrl r0;\n-\n-\tr0.val = DLB2_CSR_RD(hw, DLB2_CHP_CFG_CHP_CSR_CTRL);\n-\n-\tr0.field.cfg_64bytes_qe_dir_cq_mode = 1;\n-\n-\tDLB2_CSR_WR(hw, DLB2_CHP_CFG_CHP_CSR_CTRL, r0.val);\n-}\n-\n-void dlb2_hw_enable_sparse_ldb_cq_mode(struct dlb2_hw *hw)\n-{\n-\tunion dlb2_chp_cfg_chp_csr_ctrl r0;\n-\n-\tr0.val = DLB2_CSR_RD(hw, DLB2_CHP_CFG_CHP_CSR_CTRL);\n-\n-\tr0.field.cfg_64bytes_qe_ldb_cq_mode = 1;\n-\n-\tDLB2_CSR_WR(hw, DLB2_CHP_CFG_CHP_CSR_CTRL, r0.val);\n-}\n-\n /*\n * The PF driver cannot assume that a register write will affect subsequent HCW\n * writes. To ensure a write completes, the driver must read back a CSR. This\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_resource_new.c b/drivers/event/dlb2/pf/base/dlb2_resource_new.c\nindex 7c71fa791..f147937c0 100644\n--- a/drivers/event/dlb2/pf/base/dlb2_resource_new.c\n+++ b/drivers/event/dlb2/pf/base/dlb2_resource_new.c\n@@ -6090,3 +6090,42 @@ unsigned int dlb2_finish_map_qid_procedures(struct dlb2_hw *hw)\n \n \treturn num;\n }\n+\n+/**\n+ * dlb2_hw_enable_sparse_dir_cq_mode() - enable sparse mode for directed ports.\n+ * @hw: dlb2_hw handle for a particular device.\n+ *\n+ * This function must be called prior to configuring scheduling domains.\n+ */\n+\n+void dlb2_hw_enable_sparse_dir_cq_mode(struct dlb2_hw *hw)\n+{\n+\tu32 ctrl;\n+\n+\tctrl = DLB2_CSR_RD(hw, DLB2_CHP_CFG_CHP_CSR_CTRL);\n+\n+\tDLB2_BIT_SET(ctrl,\n+\t\t DLB2_CHP_CFG_CHP_CSR_CTRL_CFG_64BYTES_QE_DIR_CQ_MODE);\n+\n+\tDLB2_CSR_WR(hw, DLB2_CHP_CFG_CHP_CSR_CTRL, ctrl);\n+}\n+\n+/**\n+ * dlb2_hw_enable_sparse_ldb_cq_mode() - enable sparse mode for load-balanced\n+ *\tports.\n+ * @hw: dlb2_hw handle for a particular device.\n+ *\n+ * This function must be called prior to configuring scheduling domains.\n+ */\n+void dlb2_hw_enable_sparse_ldb_cq_mode(struct dlb2_hw *hw)\n+{\n+\tu32 ctrl;\n+\n+\tctrl = DLB2_CSR_RD(hw, DLB2_CHP_CFG_CHP_CSR_CTRL);\n+\n+\tDLB2_BIT_SET(ctrl,\n+\t\t DLB2_CHP_CFG_CHP_CSR_CTRL_CFG_64BYTES_QE_LDB_CQ_MODE);\n+\n+\tDLB2_CSR_WR(hw, DLB2_CHP_CFG_CHP_CSR_CTRL, ctrl);\n+}\n+\n", "prefixes": [ "16/25" ] }