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GET /api/patches/88667/?format=api
{ "id": 88667, "url": "http://patches.dpdk.org/api/patches/88667/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210306162942.6845-26-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210306162942.6845-26-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210306162942.6845-26-pbhagavatula@marvell.com", "date": "2021-03-06T16:29:30", "name": "[25/36] event/cnxk: add devargs for chunk size and rings", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a7f0407aaf59c7ba567039afcb56d2163a430834", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210306162942.6845-26-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 15516, "url": "http://patches.dpdk.org/api/series/15516/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=15516", "date": "2021-03-06T16:29:05", "name": "Marvell CNXK Event device Driver", "version": 1, "mbox": "http://patches.dpdk.org/series/15516/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/88667/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/88667/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C7B55A0548;\n\tSat, 6 Mar 2021 17:34:35 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 66EA222A4F4;\n\tSat, 6 Mar 2021 17:31:34 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 3DBD222A4BF\n for <dev@dpdk.org>; Sat, 6 Mar 2021 17:31:33 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 126GPXiJ025580 for <dev@dpdk.org>; Sat, 6 Mar 2021 08:31:32 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 3747yurey8-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Sat, 06 Mar 2021 08:31:32 -0800", "from SC-EXCH04.marvell.com (10.93.176.84) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Sat, 6 Mar 2021 08:31:31 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH04.marvell.com\n (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Sat, 6 Mar 2021 08:31:30 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Sat, 6 Mar 2021 08:31:30 -0800", "from BG-LT7430.marvell.com (unknown [10.193.68.121])\n by maili.marvell.com (Postfix) with ESMTP id A06743F7041;\n Sat, 6 Mar 2021 08:31:28 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=j/KkbPv/PWB2peH2dpweqkQv/0yGZCGk0u9cNJd197k=;\n b=UMBJsj3LT2OFo3sA+JtLluZ66BN6Uz9kRmN/BfcZ2DHzDEupfEQA2j1F0hRjCDwwkcbr\n pmybjvyDyFL+3DnFgcsGpR+VfU29LhHHqH9x8us0PpBA4QyalyzJ2L5DLLXPz+LI11J6\n JramENwotD+mKKHKM42VpTzqkoPVdQqZHX0auPi8XhjGBjT/pan/ctVEyRrqzcakVVx9\n HNokaYZWFaAugjFOOSk4R8I+tcssOPMZJ78c2Zza7QWzwcc2Y0+EuPqQFUmLXjM9Eu6I\n pB/OiyATqFpX1cJagejo536+MAWEwREVA76xXtLwd2RvahFyXzWHmt2C6C2SUHOo503p rw==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>, \"Shijith\n Thotton\" <sthotton@marvell.com>", "CC": "<ndabilpuram@marvell.com>, <dev@dpdk.org>", "Date": "Sat, 6 Mar 2021 21:59:30 +0530", "Message-ID": "<20210306162942.6845-26-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210306162942.6845-1-pbhagavatula@marvell.com>", "References": "<20210306162942.6845-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-03-06_08:2021-03-03,\n 2021-03-06 signatures=0", "Subject": "[dpdk-dev] [PATCH 25/36] event/cnxk: add devargs for chunk size and\n rings", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Shijith Thotton <sthotton@marvell.com>\n\nAdd devargs to control default chunk size and max numbers of\ntimer rings to attach to a given RVU PF.\n\nExample:\n\t--dev \"0002:1e:00.0,tim_chnk_slots=1024\"\n\t--dev \"0002:1e:00.0,tim_rings_lmt=4\"\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\nSigned-off-by: Shijith Thotton <sthotton@marvell.com>\n---\n doc/guides/eventdevs/cnxk.rst | 23 +++++++++++++++++++++++\n drivers/event/cnxk/cn10k_eventdev.c | 4 +++-\n drivers/event/cnxk/cn9k_eventdev.c | 4 +++-\n drivers/event/cnxk/cnxk_tim_evdev.c | 14 +++++++++++++-\n drivers/event/cnxk/cnxk_tim_evdev.h | 4 ++++\n 5 files changed, 46 insertions(+), 3 deletions(-)", "diff": "diff --git a/doc/guides/eventdevs/cnxk.rst b/doc/guides/eventdevs/cnxk.rst\nindex 9e14f99f2..05dcf06f4 100644\n--- a/doc/guides/eventdevs/cnxk.rst\n+++ b/doc/guides/eventdevs/cnxk.rst\n@@ -103,6 +103,29 @@ Runtime Config Options\n \n -a 0002:0e:00.0,tim_disable_npa=1\n \n+- ``TIM modify chunk slots``\n+\n+ The ``tim_chnk_slots`` devargs can be used to modify number of chunk slots.\n+ Chunks are used to store event timers, a chunk can be visualised as an array\n+ where the last element points to the next chunk and rest of them are used to\n+ store events. TIM traverses the list of chunks and enqueues the event timers\n+ to SSO. The default value is 255 and the max value is 4095.\n+\n+ For example::\n+\n+ -a 0002:0e:00.0,tim_chnk_slots=1023\n+\n+- ``TIM limit max rings reserved``\n+\n+ The ``tim_rings_lmt`` devargs can be used to limit the max number of TIM\n+ rings i.e. event timer adapter reserved on probe. Since, TIM rings are HW\n+ resources we can avoid starving other applications by not grabbing all the\n+ rings.\n+\n+ For example::\n+\n+ -a 0002:0e:00.0,tim_rings_lmt=5\n+\n Debugging Options\n -----------------\n \ndiff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c\nindex 807e666d3..a5a614196 100644\n--- a/drivers/event/cnxk/cn10k_eventdev.c\n+++ b/drivers/event/cnxk/cn10k_eventdev.c\n@@ -503,4 +503,6 @@ RTE_PMD_REGISTER_KMOD_DEP(event_cn10k, \"vfio-pci\");\n RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT \"=<int>\"\n \t\t\t CNXK_SSO_GGRP_QOS \"=<string>\"\n \t\t\t CN10K_SSO_GW_MODE \"=<int>\"\n-\t\t\t CNXK_TIM_DISABLE_NPA \"=1\");\n+\t\t\t CNXK_TIM_DISABLE_NPA \"=1\"\n+\t\t\t CNXK_TIM_CHNK_SLOTS \"=<int>\"\n+\t\t\t CNXK_TIM_RINGS_LMT \"=<int>\");\ndiff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c\nindex 3e27fce4a..cfea3723a 100644\n--- a/drivers/event/cnxk/cn9k_eventdev.c\n+++ b/drivers/event/cnxk/cn9k_eventdev.c\n@@ -572,4 +572,6 @@ RTE_PMD_REGISTER_KMOD_DEP(event_cn9k, \"vfio-pci\");\n RTE_PMD_REGISTER_PARAM_STRING(event_cn9k, CNXK_SSO_XAE_CNT \"=<int>\"\n \t\t\t CNXK_SSO_GGRP_QOS \"=<string>\"\n \t\t\t CN9K_SSO_SINGLE_WS \"=1\"\n-\t\t\t CNXK_TIM_DISABLE_NPA \"=1\");\n+\t\t\t CNXK_TIM_DISABLE_NPA \"=1\"\n+\t\t\t CNXK_TIM_CHNK_SLOTS \"=<int>\"\n+\t\t\t CNXK_TIM_RINGS_LMT \"=<int>\");\ndiff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c\nindex 6bbfadb25..07ec57fd2 100644\n--- a/drivers/event/cnxk/cnxk_tim_evdev.c\n+++ b/drivers/event/cnxk/cnxk_tim_evdev.c\n@@ -253,6 +253,10 @@ cnxk_tim_parse_devargs(struct rte_devargs *devargs, struct cnxk_tim_evdev *dev)\n \n \trte_kvargs_process(kvlist, CNXK_TIM_DISABLE_NPA, &parse_kvargs_flag,\n \t\t\t &dev->disable_npa);\n+\trte_kvargs_process(kvlist, CNXK_TIM_CHNK_SLOTS, &parse_kvargs_value,\n+\t\t\t &dev->chunk_slots);\n+\trte_kvargs_process(kvlist, CNXK_TIM_RINGS_LMT, &parse_kvargs_value,\n+\t\t\t &dev->min_ring_cnt);\n \n \trte_kvargs_free(kvlist);\n }\n@@ -278,6 +282,7 @@ cnxk_tim_init(struct roc_sso *sso)\n \tcnxk_tim_parse_devargs(sso->pci_dev->device.devargs, dev);\n \n \tdev->tim.roc_sso = sso;\n+\tdev->tim.nb_lfs = dev->min_ring_cnt;\n \trc = roc_tim_init(&dev->tim);\n \tif (rc < 0) {\n \t\tplt_err(\"Failed to initialize roc tim resources\");\n@@ -285,7 +290,14 @@ cnxk_tim_init(struct roc_sso *sso)\n \t\treturn;\n \t}\n \tdev->nb_rings = rc;\n-\tdev->chunk_sz = CNXK_TIM_RING_DEF_CHUNK_SZ;\n+\n+\tif (dev->chunk_slots && dev->chunk_slots <= CNXK_TIM_MAX_CHUNK_SLOTS &&\n+\t dev->chunk_slots >= CNXK_TIM_MIN_CHUNK_SLOTS) {\n+\t\tdev->chunk_sz =\n+\t\t\t(dev->chunk_slots + 1) * CNXK_TIM_CHUNK_ALIGNMENT;\n+\t} else {\n+\t\tdev->chunk_sz = CNXK_TIM_RING_DEF_CHUNK_SZ;\n+\t}\n }\n \n void\ndiff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h\nindex 8c21ab1fe..6208c150a 100644\n--- a/drivers/event/cnxk/cnxk_tim_evdev.h\n+++ b/drivers/event/cnxk/cnxk_tim_evdev.h\n@@ -34,6 +34,8 @@\n #define CN9K_TIM_MIN_TMO_TKS (256)\n \n #define CNXK_TIM_DISABLE_NPA \"tim_disable_npa\"\n+#define CNXK_TIM_CHNK_SLOTS \"tim_chnk_slots\"\n+#define CNXK_TIM_RINGS_LMT \"tim_rings_lmt\"\n \n struct cnxk_tim_evdev {\n \tstruct roc_tim tim;\n@@ -42,6 +44,8 @@ struct cnxk_tim_evdev {\n \tuint32_t chunk_sz;\n \t/* Dev args */\n \tuint8_t disable_npa;\n+\tuint16_t chunk_slots;\n+\tuint16_t min_ring_cnt;\n };\n \n enum cnxk_tim_clk_src {\n", "prefixes": [ "25/36" ] }