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GET /api/patches/88661/?format=api
{ "id": 88661, "url": "http://patches.dpdk.org/api/patches/88661/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210306162942.6845-20-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210306162942.6845-20-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210306162942.6845-20-pbhagavatula@marvell.com", "date": "2021-03-06T16:29:24", "name": "[19/36] event/cnxk: support event timer", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "de42af4959201626da21daa4d14e6d7f9f40f269", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210306162942.6845-20-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 15516, "url": "http://patches.dpdk.org/api/series/15516/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=15516", "date": "2021-03-06T16:29:05", "name": "Marvell CNXK Event device Driver", "version": 1, "mbox": "http://patches.dpdk.org/series/15516/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/88661/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/88661/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C515DA0548;\n\tSat, 6 Mar 2021 17:33:34 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 61C3B22A4DA;\n\tSat, 6 Mar 2021 17:31:18 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 17A3D22A4DA\n for <dev@dpdk.org>; Sat, 6 Mar 2021 17:31:16 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 126GQjLP009184; Sat, 6 Mar 2021 08:31:15 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 374a4w08qf-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Sat, 06 Mar 2021 08:31:15 -0800", "from SC-EXCH03.marvell.com (10.93.176.83) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Sat, 6 Mar 2021 08:31:13 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH03.marvell.com\n (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Sat, 6 Mar 2021 08:31:13 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Sat, 6 Mar 2021 08:31:13 -0800", "from BG-LT7430.marvell.com (unknown [10.193.68.121])\n by maili.marvell.com (Postfix) with ESMTP id E0C643F7041;\n Sat, 6 Mar 2021 08:31:10 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=tGeTJT1amWOg4UmjLkXZ2Yao9g3z0gO5Nvpdi3cfsVg=;\n b=RweAkdmR72EYE75TiLN2+xBitNZO1Rqr/zM6P7KGmXSx67RQPMHetnyC29MwyO3+nYqE\n YeMIRKhrkiOyKzaC7OzPgjGSISpkkC3T20+sRC6HGWS0XzNAARnPcdMRjDeqlPXV42eT\n 1RkkfZ8QgjytP89tHOGzB9N0GbiZgYysaa9DCa5lvrAg5RWUlsSAtfLzJU4dSAY8nmam\n 9PNz4FbxCFbi9c7/tG4WUPug/Dm6YSl+vOWAVvThar0WVAOG2UOrxcyNetdejAkke2gI\n UrjMvv+Ki7bwkTHR86WOdrwRnKbK414oGAgKG5Hx8Ks1gX1+WdWpV9lJ1XU3UcDAJp+R Nw==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>, \"Shijith\n Thotton\" <sthotton@marvell.com>,\n Anatoly Burakov <anatoly.burakov@intel.com>", "CC": "<ndabilpuram@marvell.com>, <dev@dpdk.org>", "Date": "Sat, 6 Mar 2021 21:59:24 +0530", "Message-ID": "<20210306162942.6845-20-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210306162942.6845-1-pbhagavatula@marvell.com>", "References": "<20210306162942.6845-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-03-06_08:2021-03-03,\n 2021-03-06 signatures=0", "Subject": "[dpdk-dev] [PATCH 19/36] event/cnxk: support event timer", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Shijith Thotton <sthotton@marvell.com>\n\nAdd event timer adapter aka TIM initialization on SSO probe.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\nSigned-off-by: Shijith Thotton <sthotton@marvell.com>\n---\n doc/guides/eventdevs/cnxk.rst | 6 ++++\n drivers/event/cnxk/cnxk_eventdev.c | 3 ++\n drivers/event/cnxk/cnxk_eventdev.h | 2 ++\n drivers/event/cnxk/cnxk_tim_evdev.c | 47 +++++++++++++++++++++++++++++\n drivers/event/cnxk/cnxk_tim_evdev.h | 44 +++++++++++++++++++++++++++\n drivers/event/cnxk/meson.build | 3 +-\n 6 files changed, 104 insertions(+), 1 deletion(-)\n create mode 100644 drivers/event/cnxk/cnxk_tim_evdev.c\n create mode 100644 drivers/event/cnxk/cnxk_tim_evdev.h", "diff": "diff --git a/doc/guides/eventdevs/cnxk.rst b/doc/guides/eventdevs/cnxk.rst\nindex b2684d431..662df2971 100644\n--- a/doc/guides/eventdevs/cnxk.rst\n+++ b/doc/guides/eventdevs/cnxk.rst\n@@ -35,6 +35,10 @@ Features of the OCTEON CNXK SSO PMD are:\n - Open system with configurable amount of outstanding events limited only by\n DRAM\n - HW accelerated dequeue timeout support to enable power management\n+- HW managed event timers support through TIM, with high precision and\n+ time granularity of 2.5us on CN9K and 1us on CN10K.\n+- Up to 256 TIM rings aka event timer adapters.\n+- Up to 8 rings traversed in parallel.\n \n Prerequisites and Compilation procedure\n ---------------------------------------\n@@ -101,3 +105,5 @@ Debugging Options\n +===+============+=======================================================+\n | 1 | SSO | --log-level='pmd\\.event\\.cnxk,8' |\n +---+------------+-------------------------------------------------------+\n+ | 2 | TIM | --log-level='pmd\\.event\\.cnxk\\.timer,8' |\n+ +---+------------+-------------------------------------------------------+\ndiff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c\nindex dbd35ca5d..c404bb586 100644\n--- a/drivers/event/cnxk/cnxk_eventdev.c\n+++ b/drivers/event/cnxk/cnxk_eventdev.c\n@@ -582,6 +582,8 @@ cnxk_sso_init(struct rte_eventdev *event_dev)\n \tdev->nb_event_queues = 0;\n \tdev->nb_event_ports = 0;\n \n+\tcnxk_tim_init(&dev->sso);\n+\n \treturn 0;\n \n error:\n@@ -598,6 +600,7 @@ cnxk_sso_fini(struct rte_eventdev *event_dev)\n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n \t\treturn 0;\n \n+\tcnxk_tim_fini();\n \troc_sso_rsrc_fini(&dev->sso);\n \troc_sso_dev_fini(&dev->sso);\n \ndiff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h\nindex ee7dce5f5..e4051a64b 100644\n--- a/drivers/event/cnxk/cnxk_eventdev.h\n+++ b/drivers/event/cnxk/cnxk_eventdev.h\n@@ -14,6 +14,8 @@\n \n #include \"roc_api.h\"\n \n+#include \"cnxk_tim_evdev.h\"\n+\n #define CNXK_SSO_XAE_CNT \"xae_cnt\"\n #define CNXK_SSO_GGRP_QOS \"qos\"\n #define CN9K_SSO_SINGLE_WS \"single_ws\"\ndiff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c\nnew file mode 100644\nindex 000000000..76b17910f\n--- /dev/null\n+++ b/drivers/event/cnxk/cnxk_tim_evdev.c\n@@ -0,0 +1,47 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell International Ltd.\n+ */\n+\n+#include \"cnxk_eventdev.h\"\n+#include \"cnxk_tim_evdev.h\"\n+\n+void\n+cnxk_tim_init(struct roc_sso *sso)\n+{\n+\tconst struct rte_memzone *mz;\n+\tstruct cnxk_tim_evdev *dev;\n+\tint rc;\n+\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n+\t\treturn;\n+\n+\tmz = rte_memzone_reserve(RTE_STR(CNXK_TIM_EVDEV_NAME),\n+\t\t\t\t sizeof(struct cnxk_tim_evdev), 0, 0);\n+\tif (mz == NULL) {\n+\t\tplt_tim_dbg(\"Unable to allocate memory for TIM Event device\");\n+\t\treturn;\n+\t}\n+\tdev = mz->addr;\n+\n+\tdev->tim.roc_sso = sso;\n+\trc = roc_tim_init(&dev->tim);\n+\tif (rc < 0) {\n+\t\tplt_err(\"Failed to initialize roc tim resources\");\n+\t\trte_memzone_free(mz);\n+\t\treturn;\n+\t}\n+\tdev->nb_rings = rc;\n+\tdev->chunk_sz = CNXK_TIM_RING_DEF_CHUNK_SZ;\n+}\n+\n+void\n+cnxk_tim_fini(void)\n+{\n+\tstruct cnxk_tim_evdev *dev = tim_priv_get();\n+\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n+\t\treturn;\n+\n+\troc_tim_fini(&dev->tim);\n+\trte_memzone_free(rte_memzone_lookup(RTE_STR(CNXK_TIM_EVDEV_NAME)));\n+}\ndiff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h\nnew file mode 100644\nindex 000000000..6cf0adb21\n--- /dev/null\n+++ b/drivers/event/cnxk/cnxk_tim_evdev.h\n@@ -0,0 +1,44 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell International Ltd.\n+ */\n+\n+#ifndef __CNXK_TIM_EVDEV_H__\n+#define __CNXK_TIM_EVDEV_H__\n+\n+#include <stddef.h>\n+#include <stdint.h>\n+#include <stdlib.h>\n+#include <string.h>\n+\n+#include <eventdev_pmd_pci.h>\n+#include <rte_event_timer_adapter.h>\n+#include <rte_memzone.h>\n+\n+#include \"roc_api.h\"\n+\n+#define CNXK_TIM_EVDEV_NAME\t cnxk_tim_eventdev\n+#define CNXK_TIM_RING_DEF_CHUNK_SZ (4096)\n+\n+struct cnxk_tim_evdev {\n+\tstruct roc_tim tim;\n+\tstruct rte_eventdev *event_dev;\n+\tuint16_t nb_rings;\n+\tuint32_t chunk_sz;\n+};\n+\n+static inline struct cnxk_tim_evdev *\n+tim_priv_get(void)\n+{\n+\tconst struct rte_memzone *mz;\n+\n+\tmz = rte_memzone_lookup(RTE_STR(CNXK_TIM_EVDEV_NAME));\n+\tif (mz == NULL)\n+\t\treturn NULL;\n+\n+\treturn mz->addr;\n+}\n+\n+void cnxk_tim_init(struct roc_sso *sso);\n+void cnxk_tim_fini(void);\n+\n+#endif /* __CNXK_TIM_EVDEV_H__ */\ndiff --git a/drivers/event/cnxk/meson.build b/drivers/event/cnxk/meson.build\nindex 8bac4b7f3..6e9f3daab 100644\n--- a/drivers/event/cnxk/meson.build\n+++ b/drivers/event/cnxk/meson.build\n@@ -13,6 +13,7 @@ sources = files('cn10k_worker.c',\n \t\t'cn9k_worker.c',\n \t\t'cn9k_eventdev.c',\n \t\t'cnxk_eventdev.c',\n-\t\t'cnxk_sso_selftest.c')\n+\t\t'cnxk_sso_selftest.c',\n+\t\t'cnxk_tim_evdev.c')\n \n deps += ['bus_pci', 'common_cnxk', 'net_cnxk']\n", "prefixes": [ "19/36" ] }