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GET /api/patches/88650/?format=api
{ "id": 88650, "url": "http://patches.dpdk.org/api/patches/88650/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210306162942.6845-9-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210306162942.6845-9-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210306162942.6845-9-pbhagavatula@marvell.com", "date": "2021-03-06T16:29:13", "name": "[08/36] event/cnxk: add devargs for inflight buffer count", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d79d05976a9b07266c7759ee5ce3d63c7b9a4c71", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210306162942.6845-9-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 15516, "url": "http://patches.dpdk.org/api/series/15516/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=15516", "date": "2021-03-06T16:29:05", "name": "Marvell CNXK Event device Driver", "version": 1, "mbox": "http://patches.dpdk.org/series/15516/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/88650/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/88650/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 71D6BA0548;\n\tSat, 6 Mar 2021 17:31:24 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 0EE0622A44F;\n\tSat, 6 Mar 2021 17:30:43 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 59B7922A421\n for <dev@dpdk.org>; Sat, 6 Mar 2021 17:30:41 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 126GR9n2027849 for <dev@dpdk.org>; Sat, 6 Mar 2021 08:30:40 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 3747yurevu-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Sat, 06 Mar 2021 08:30:40 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Sat, 6 Mar 2021 08:30:39 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Sat, 6 Mar 2021 08:30:39 -0800", "from BG-LT7430.marvell.com (unknown [10.193.68.121])\n by maili.marvell.com (Postfix) with ESMTP id 421623F7043;\n Sat, 6 Mar 2021 08:30:37 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=gf/iHZvgxfWEhSNtyXSBrpEeclvFmHe6Nwzv2fZoK3c=;\n b=TepxgnB8Lt6hxEy2oGH52oEsWjLSptcAo3B+ChjqfzRsLnP34jT9qn+UzSkOC6SEIjGb\n F0/BotTu1hXmG1qv8Z93bwtoiR+mUFDgaRBIsHmtqEXHBTzj0hC1TgVSzkC1MGO1UyXN\n Kn2nEWpvssBjrsnUzQXqDJRakpIITrtlqvGDi9SDADoWsAfkBR41UFctrd8nWKorS/TS\n id5/ELHoDqVuelJxtfSSndSnK2+jEbALjq1mOy20jqca4lYUEMbbl2Qg9RngcMg5XDWS\n CB2iYF+pU6RI4pyoyTfuHqapYhkZ2MPWMqI4oMrgIYb8o9eGEPXpScKdOeXlv9paeuCv vg==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>, \"Shijith\n Thotton\" <sthotton@marvell.com>", "CC": "<ndabilpuram@marvell.com>, <dev@dpdk.org>", "Date": "Sat, 6 Mar 2021 21:59:13 +0530", "Message-ID": "<20210306162942.6845-9-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210306162942.6845-1-pbhagavatula@marvell.com>", "References": "<20210306162942.6845-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-03-06_08:2021-03-03,\n 2021-03-06 signatures=0", "Subject": "[dpdk-dev] [PATCH 08/36] event/cnxk: add devargs for inflight\n buffer count", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Shijith Thotton <sthotton@marvell.com>\n\nThe number of events for a *open system* event device is specified\nas -1 as per the eventdev specification.\nSince, SSO inflight events are only limited by DRAM size, the\nxae_cnt devargs parameter is introduced to provide upper limit for\nin-flight events.\n\nExample:\n --dev \"0002:0e:00.0,xae_cnt=8192\"\n\nSigned-off-by: Shijith Thotton <sthotton@marvell.com>\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n doc/guides/eventdevs/cnxk.rst | 14 ++++++++++++++\n drivers/event/cnxk/cn10k_eventdev.c | 1 +\n drivers/event/cnxk/cn9k_eventdev.c | 1 +\n drivers/event/cnxk/cnxk_eventdev.c | 24 ++++++++++++++++++++++--\n drivers/event/cnxk/cnxk_eventdev.h | 15 +++++++++++++++\n 5 files changed, 53 insertions(+), 2 deletions(-)", "diff": "diff --git a/doc/guides/eventdevs/cnxk.rst b/doc/guides/eventdevs/cnxk.rst\nindex e94225bd3..569fce4cb 100644\n--- a/doc/guides/eventdevs/cnxk.rst\n+++ b/doc/guides/eventdevs/cnxk.rst\n@@ -41,6 +41,20 @@ Prerequisites and Compilation procedure\n \n See :doc:`../platform/cnxk` for setup information.\n \n+\n+Runtime Config Options\n+----------------------\n+\n+- ``Maximum number of in-flight events`` (default ``8192``)\n+\n+ In **Marvell OCTEON CNXK** the max number of in-flight events are only limited\n+ by DRAM size, the ``xae_cnt`` devargs parameter is introduced to provide\n+ upper limit for in-flight events.\n+\n+ For example::\n+\n+ -a 0002:0e:00.0,xae_cnt=16384\n+\n Debugging Options\n -----------------\n \ndiff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c\nindex 7e3fa20c5..1b278360f 100644\n--- a/drivers/event/cnxk/cn10k_eventdev.c\n+++ b/drivers/event/cnxk/cn10k_eventdev.c\n@@ -143,3 +143,4 @@ static struct rte_pci_driver cn10k_pci_sso = {\n RTE_PMD_REGISTER_PCI(event_cn10k, cn10k_pci_sso);\n RTE_PMD_REGISTER_PCI_TABLE(event_cn10k, cn10k_pci_sso_map);\n RTE_PMD_REGISTER_KMOD_DEP(event_cn10k, \"vfio-pci\");\n+RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT \"=<int>\");\ndiff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c\nindex 71245b660..8dfcf35b4 100644\n--- a/drivers/event/cnxk/cn9k_eventdev.c\n+++ b/drivers/event/cnxk/cn9k_eventdev.c\n@@ -146,3 +146,4 @@ static struct rte_pci_driver cn9k_pci_sso = {\n RTE_PMD_REGISTER_PCI(event_cn9k, cn9k_pci_sso);\n RTE_PMD_REGISTER_PCI_TABLE(event_cn9k, cn9k_pci_sso_map);\n RTE_PMD_REGISTER_KMOD_DEP(event_cn9k, \"vfio-pci\");\n+RTE_PMD_REGISTER_PARAM_STRING(event_cn9k, CNXK_SSO_XAE_CNT \"=<int>\");\ndiff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c\nindex 927f99117..28a03aeab 100644\n--- a/drivers/event/cnxk/cnxk_eventdev.c\n+++ b/drivers/event/cnxk/cnxk_eventdev.c\n@@ -75,8 +75,11 @@ cnxk_sso_xaq_allocate(struct cnxk_sso_evdev *dev)\n \n \t/* Taken from HRM 14.3.3(4) */\n \txaq_cnt = dev->nb_event_queues * CNXK_SSO_XAQ_CACHE_CNT;\n-\txaq_cnt += (dev->sso.iue / dev->sso.xae_waes) +\n-\t\t (CNXK_SSO_XAQ_SLACK * dev->nb_event_queues);\n+\tif (dev->xae_cnt)\n+\t\txaq_cnt += dev->xae_cnt / dev->sso.xae_waes;\n+\telse\n+\t\txaq_cnt += (dev->sso.iue / dev->sso.xae_waes) +\n+\t\t\t (CNXK_SSO_XAQ_SLACK * dev->nb_event_queues);\n \n \tplt_sso_dbg(\"Configuring %d xaq buffers\", xaq_cnt);\n \t/* Setup XAQ based on number of nb queues. */\n@@ -222,6 +225,22 @@ cnxk_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id,\n \tport_conf->enqueue_depth = 1;\n }\n \n+static void\n+cnxk_sso_parse_devargs(struct cnxk_sso_evdev *dev, struct rte_devargs *devargs)\n+{\n+\tstruct rte_kvargs *kvlist;\n+\n+\tif (devargs == NULL)\n+\t\treturn;\n+\tkvlist = rte_kvargs_parse(devargs->args, NULL);\n+\tif (kvlist == NULL)\n+\t\treturn;\n+\n+\trte_kvargs_process(kvlist, CNXK_SSO_XAE_CNT, &parse_kvargs_value,\n+\t\t\t &dev->xae_cnt);\n+\trte_kvargs_free(kvlist);\n+}\n+\n int\n cnxk_sso_init(struct rte_eventdev *event_dev)\n {\n@@ -242,6 +261,7 @@ cnxk_sso_init(struct rte_eventdev *event_dev)\n \tdev->sso.pci_dev = pci_dev;\n \n \t*(uint64_t *)mz->addr = (uint64_t)dev;\n+\tcnxk_sso_parse_devargs(dev, pci_dev->device.devargs);\n \n \t/* Initialize the base cnxk_dev object */\n \trc = roc_sso_dev_init(&dev->sso);\ndiff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h\nindex 8478120c0..72b0ff3f8 100644\n--- a/drivers/event/cnxk/cnxk_eventdev.h\n+++ b/drivers/event/cnxk/cnxk_eventdev.h\n@@ -5,6 +5,8 @@\n #ifndef __CNXK_EVENTDEV_H__\n #define __CNXK_EVENTDEV_H__\n \n+#include <rte_devargs.h>\n+#include <rte_kvargs.h>\n #include <rte_mbuf_pool_ops.h>\n #include <rte_pci.h>\n \n@@ -12,6 +14,8 @@\n \n #include \"roc_api.h\"\n \n+#define CNXK_SSO_XAE_CNT \"xae_cnt\"\n+\n #define USEC2NSEC(__us) ((__us)*1E3)\n \n #define CNXK_SSO_FC_NAME \"cnxk_evdev_xaq_fc\"\n@@ -35,10 +39,21 @@ struct cnxk_sso_evdev {\n \tuint64_t nb_xaq_cfg;\n \trte_iova_t fc_iova;\n \tstruct rte_mempool *xaq_pool;\n+\t/* Dev args */\n+\tuint32_t xae_cnt;\n \t/* CN9K */\n \tuint8_t dual_ws;\n } __rte_cache_aligned;\n \n+static inline int\n+parse_kvargs_value(const char *key, const char *value, void *opaque)\n+{\n+\tRTE_SET_USED(key);\n+\n+\t*(uint32_t *)opaque = (uint32_t)atoi(value);\n+\treturn 0;\n+}\n+\n static inline struct cnxk_sso_evdev *\n cnxk_sso_pmd_priv(const struct rte_eventdev *event_dev)\n {\n", "prefixes": [ "08/36" ] }