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GET /api/patches/88600/?format=api
{ "id": 88600, "url": "http://patches.dpdk.org/api/patches/88600/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210306153404.10781-4-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210306153404.10781-4-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210306153404.10781-4-ndabilpuram@marvell.com", "date": "2021-03-06T15:33:23", "name": "[03/44] net/cnxk: add common devargs parsing function", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "01822165ba718391ec25ad6868a6921a37008c11", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210306153404.10781-4-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 15515, "url": "http://patches.dpdk.org/api/series/15515/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=15515", "date": "2021-03-06T15:33:20", "name": "Marvell CNXK Ethdev Driver", "version": 1, "mbox": "http://patches.dpdk.org/series/15515/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/88600/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/88600/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8E44CA0548;\n\tSat, 6 Mar 2021 16:34:42 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 516C422A35B;\n\tSat, 6 Mar 2021 16:34:27 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 360674014D\n for <dev@dpdk.org>; Sat, 6 Mar 2021 16:34:25 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 126FVquf029350 for <dev@dpdk.org>; Sat, 6 Mar 2021 07:34:24 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com with ESMTP id 3747yurcad-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Sat, 06 Mar 2021 07:34:24 -0800", "from SC-EXCH03.marvell.com (10.93.176.83) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Sat, 6 Mar 2021 07:34:22 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH03.marvell.com\n (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Sat, 6 Mar 2021 07:34:22 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Sat, 6 Mar 2021 07:34:22 -0800", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id BFC3C3F703F;\n Sat, 6 Mar 2021 07:34:19 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=b1rIIEMu/wmydCmuI4rbYtMvcewvozjAExa3fxOPzRY=;\n b=jPl84677drliXLA4n0FCv9xDn6wW33UJa/PUIm/11qzWmiHC9GHJJGM3LLszjGkusytL\n 5teweFNQUMF7Kklz85p9LMUkmxeLPhD5yvqR4R7WI0D72r6N01rfEmpmP9cz5C7uPASZ\n rgfvzx6zPc8d7ufrubk6h/aPuUU/WOR0HO9Nn1vBkih9fDo0zSOHi2CboAuKiKC6M8NA\n OZrNVsL5dr/+3PX3a0lJG6d0AEzyTqCnZgRmfoqIUlIZWg3d8/zSn4sXJgvqTsAm8gxw\n Yn54z6gvnFIuTqvY4yXgTCuIp9owuqStLnSk+I/QlYjaiDQeX5dJTCdMJAAAtSfGfFtN Mg==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>, Nithin Dabilpuram\n <ndabilpuram@marvell.com>", "Date": "Sat, 6 Mar 2021 21:03:23 +0530", "Message-ID": "<20210306153404.10781-4-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210306153404.10781-1-ndabilpuram@marvell.com>", "References": "<20210306153404.10781-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-03-06_08:2021-03-03,\n 2021-03-06 signatures=0", "Subject": "[dpdk-dev] [PATCH 03/44] net/cnxk: add common devargs parsing\n function", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add various devargs parsing command line arguments\nparsing functions supported by CN9K and CN10K.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n doc/guides/nics/cnxk.rst | 94 +++++++++++++++++++\n drivers/net/cnxk/cnxk_ethdev.c | 7 ++\n drivers/net/cnxk/cnxk_ethdev.h | 9 ++\n drivers/net/cnxk/cnxk_ethdev_devargs.c | 166 +++++++++++++++++++++++++++++++++\n drivers/net/cnxk/meson.build | 3 +-\n 5 files changed, 278 insertions(+), 1 deletion(-)\n create mode 100644 drivers/net/cnxk/cnxk_ethdev_devargs.c", "diff": "diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst\nindex ca21842..611ffb4 100644\n--- a/doc/guides/nics/cnxk.rst\n+++ b/doc/guides/nics/cnxk.rst\n@@ -27,3 +27,97 @@ Driver compilation and testing\n \n Refer to the document :ref:`compiling and testing a PMD for a NIC <pmd_build_and_test>`\n for details.\n+\n+Runtime Config Options\n+----------------------\n+\n+- ``Rx&Tx scalar mode enable`` (default ``0``)\n+\n+ Ethdev supports both scalar and vector mode, it may be selected at runtime\n+ using ``scalar_enable`` ``devargs`` parameter.\n+\n+- ``RSS reta size`` (default ``64``)\n+\n+ RSS redirection table size may be configured during runtime using ``reta_size``\n+ ``devargs`` parameter.\n+\n+ For example::\n+\n+ -a 0002:02:00.0,reta_size=256\n+\n+ With the above configuration, reta table of size 256 is populated.\n+\n+- ``Flow priority levels`` (default ``3``)\n+\n+ RTE Flow priority levels can be configured during runtime using\n+ ``flow_max_priority`` ``devargs`` parameter.\n+\n+ For example::\n+\n+ -a 0002:02:00.0,flow_max_priority=10\n+\n+ With the above configuration, priority level was set to 10 (0-9). Max\n+ priority level supported is 32.\n+\n+- ``Reserve Flow entries`` (default ``8``)\n+\n+ RTE flow entries can be pre allocated and the size of pre allocation can be\n+ selected runtime using ``flow_prealloc_size`` ``devargs`` parameter.\n+\n+ For example::\n+\n+ -a 0002:02:00.0,flow_prealloc_size=4\n+\n+ With the above configuration, pre alloc size was set to 4. Max pre alloc\n+ size supported is 32.\n+\n+- ``Max SQB buffer count`` (default ``512``)\n+\n+ Send queue descriptor buffer count may be limited during runtime using\n+ ``max_sqb_count`` ``devargs`` parameter.\n+\n+ For example::\n+\n+ -a 0002:02:00.0,max_sqb_count=64\n+\n+ With the above configuration, each send queue's decscriptor buffer count is\n+ limited to a maximum of 64 buffers.\n+\n+- ``Switch header enable`` (default ``none``)\n+\n+ A port can be configured to a specific switch header type by using\n+ ``switch_header`` ``devargs`` parameter.\n+\n+ For example::\n+\n+ -a 0002:02:00.0,switch_header=\"higig2\"\n+\n+ With the above configuration, higig2 will be enabled on that port and the\n+ traffic on this port should be higig2 traffic only. Supported switch header\n+ types are \"higig2\", \"dsa\", \"chlen90b\" and \"chlen24b\".\n+\n+- ``RSS tag as XOR`` (default ``0``)\n+\n+ The HW gives two options to configure the RSS adder i.e\n+\n+ * ``rss_adder<7:0> = flow_tag<7:0> ^ flow_tag<15:8> ^ flow_tag<23:16> ^ flow_tag<31:24>``\n+\n+ * ``rss_adder<7:0> = flow_tag<7:0>``\n+\n+ Latter one aligns with standard NIC behavior vs former one is a legacy\n+ RSS adder scheme used in OCTEON TX2 products.\n+\n+ By default, the driver runs in the latter mode.\n+ Setting this flag to 1 to select the legacy mode.\n+\n+ For example to select the legacy mode(RSS tag adder as XOR)::\n+\n+ -a 0002:02:00.0,tag_as_xor=1\n+\n+\n+\n+.. note::\n+\n+ Above devarg parameters are configurable per device, user needs to pass the\n+ parameters to all the PCIe devices if application requires to configure on\n+ all the ethdev ports.\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c\nindex b836fc2..3a2309e 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.c\n+++ b/drivers/net/cnxk/cnxk_ethdev.c\n@@ -58,6 +58,13 @@ cnxk_eth_dev_init(struct rte_eth_dev *eth_dev)\n \trte_eth_copy_pci_info(eth_dev, pci_dev);\n \teth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;\n \n+\t/* Parse devargs string */\n+\trc = cnxk_ethdev_parse_devargs(eth_dev->device->devargs, dev);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to parse devargs rc=%d\", rc);\n+\t\tgoto error;\n+\t}\n+\n \t/* Initialize base roc nix */\n \tnix->pci_dev = pci_dev;\n \trc = roc_nix_dev_init(nix);\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h\nindex ba2bfcd..97e3a15 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.h\n+++ b/drivers/net/cnxk/cnxk_ethdev.h\n@@ -9,11 +9,15 @@\n \n #include <ethdev_driver.h>\n #include <ethdev_pci.h>\n+#include <rte_kvargs.h>\n \n #include \"roc_api.h\"\n \n #define CNXK_ETH_DEV_PMD_VERSION \"1.0\"\n \n+/* Max supported SQB count */\n+#define CNXK_NIX_TX_MAX_SQB 512\n+\n #define CNXK_NIX_TX_OFFLOAD_CAPA \\\n \t(DEV_TX_OFFLOAD_MBUF_FAST_FREE | DEV_TX_OFFLOAD_MT_LOCKFREE | \\\n \t DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT | \\\n@@ -38,6 +42,7 @@ struct cnxk_eth_dev {\n \tuint8_t max_mac_entries;\n \n \tuint16_t flags;\n+\tbool scalar_ena;\n \n \t/* Pointer back to rte */\n \tstruct rte_eth_dev *eth_dev;\n@@ -73,4 +78,8 @@ int cnxk_nix_probe(struct rte_pci_driver *pci_drv,\n \t\t struct rte_pci_device *pci_dev);\n int cnxk_nix_remove(struct rte_pci_device *pci_dev);\n \n+/* Devargs */\n+int cnxk_ethdev_parse_devargs(struct rte_devargs *devargs,\n+\t\t\t struct cnxk_eth_dev *dev);\n+\n #endif /* __CNXK_ETHDEV_H__ */\ndiff --git a/drivers/net/cnxk/cnxk_ethdev_devargs.c b/drivers/net/cnxk/cnxk_ethdev_devargs.c\nnew file mode 100644\nindex 0000000..4af2803\n--- /dev/null\n+++ b/drivers/net/cnxk/cnxk_ethdev_devargs.c\n@@ -0,0 +1,166 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include <inttypes.h>\n+#include <math.h>\n+\n+#include \"cnxk_ethdev.h\"\n+\n+static int\n+parse_flow_max_priority(const char *key, const char *value, void *extra_args)\n+{\n+\tRTE_SET_USED(key);\n+\tuint16_t val;\n+\n+\tval = atoi(value);\n+\n+\t/* Limit the max priority to 32 */\n+\tif (val < 1 || val > 32)\n+\t\treturn -EINVAL;\n+\n+\t*(uint16_t *)extra_args = val;\n+\n+\treturn 0;\n+}\n+\n+static int\n+parse_flow_prealloc_size(const char *key, const char *value, void *extra_args)\n+{\n+\tRTE_SET_USED(key);\n+\tuint16_t val;\n+\n+\tval = atoi(value);\n+\n+\t/* Limit the prealloc size to 32 */\n+\tif (val < 1 || val > 32)\n+\t\treturn -EINVAL;\n+\n+\t*(uint16_t *)extra_args = val;\n+\n+\treturn 0;\n+}\n+\n+static int\n+parse_reta_size(const char *key, const char *value, void *extra_args)\n+{\n+\tRTE_SET_USED(key);\n+\tuint32_t val;\n+\n+\tval = atoi(value);\n+\n+\tif (val <= ETH_RSS_RETA_SIZE_64)\n+\t\tval = ROC_NIX_RSS_RETA_SZ_64;\n+\telse if (val > ETH_RSS_RETA_SIZE_64 && val <= ETH_RSS_RETA_SIZE_128)\n+\t\tval = ROC_NIX_RSS_RETA_SZ_128;\n+\telse if (val > ETH_RSS_RETA_SIZE_128 && val <= ETH_RSS_RETA_SIZE_256)\n+\t\tval = ROC_NIX_RSS_RETA_SZ_256;\n+\telse\n+\t\tval = ROC_NIX_RSS_RETA_SZ_64;\n+\n+\t*(uint16_t *)extra_args = val;\n+\n+\treturn 0;\n+}\n+\n+static int\n+parse_flag(const char *key, const char *value, void *extra_args)\n+{\n+\tRTE_SET_USED(key);\n+\n+\t*(uint16_t *)extra_args = atoi(value);\n+\n+\treturn 0;\n+}\n+\n+static int\n+parse_sqb_count(const char *key, const char *value, void *extra_args)\n+{\n+\tRTE_SET_USED(key);\n+\tuint32_t val;\n+\n+\tval = atoi(value);\n+\n+\t*(uint16_t *)extra_args = val;\n+\n+\treturn 0;\n+}\n+\n+static int\n+parse_switch_header_type(const char *key, const char *value, void *extra_args)\n+{\n+\tRTE_SET_USED(key);\n+\n+\tif (strcmp(value, \"higig2\") == 0)\n+\t\t*(uint16_t *)extra_args = ROC_PRIV_FLAGS_HIGIG;\n+\n+\tif (strcmp(value, \"dsa\") == 0)\n+\t\t*(uint16_t *)extra_args = ROC_PRIV_FLAGS_EDSA;\n+\n+\tif (strcmp(value, \"chlen90b\") == 0)\n+\t\t*(uint16_t *)extra_args = ROC_PRIV_FLAGS_LEN_90B;\n+\treturn 0;\n+}\n+\n+#define CNXK_RSS_RETA_SIZE\t\"reta_size\"\n+#define CNXK_SCL_ENABLE\t\t\"scalar_enable\"\n+#define CNXK_MAX_SQB_COUNT\t\"max_sqb_count\"\n+#define CNXK_FLOW_PREALLOC_SIZE \"flow_prealloc_size\"\n+#define CNXK_FLOW_MAX_PRIORITY\t\"flow_max_priority\"\n+#define CNXK_SWITCH_HEADER_TYPE \"switch_header\"\n+#define CNXK_RSS_TAG_AS_XOR\t\"tag_as_xor\"\n+\n+int\n+cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev)\n+{\n+\tuint16_t reta_sz = ROC_NIX_RSS_RETA_SZ_64;\n+\tuint16_t sqb_count = CNXK_NIX_TX_MAX_SQB;\n+\tuint16_t flow_prealloc_size = 8;\n+\tuint16_t switch_header_type = 0;\n+\tuint16_t flow_max_priority = 3;\n+\tuint16_t rss_tag_as_xor = 0;\n+\tuint16_t scalar_enable = 0;\n+\tstruct rte_kvargs *kvlist;\n+\n+\tif (devargs == NULL)\n+\t\tgoto null_devargs;\n+\n+\tkvlist = rte_kvargs_parse(devargs->args, NULL);\n+\tif (kvlist == NULL)\n+\t\tgoto exit;\n+\n+\trte_kvargs_process(kvlist, CNXK_RSS_RETA_SIZE, &parse_reta_size,\n+\t\t\t &reta_sz);\n+\trte_kvargs_process(kvlist, CNXK_SCL_ENABLE, &parse_flag,\n+\t\t\t &scalar_enable);\n+\trte_kvargs_process(kvlist, CNXK_MAX_SQB_COUNT, &parse_sqb_count,\n+\t\t\t &sqb_count);\n+\trte_kvargs_process(kvlist, CNXK_FLOW_PREALLOC_SIZE,\n+\t\t\t &parse_flow_prealloc_size, &flow_prealloc_size);\n+\trte_kvargs_process(kvlist, CNXK_FLOW_MAX_PRIORITY,\n+\t\t\t &parse_flow_max_priority, &flow_max_priority);\n+\trte_kvargs_process(kvlist, CNXK_SWITCH_HEADER_TYPE,\n+\t\t\t &parse_switch_header_type, &switch_header_type);\n+\trte_kvargs_process(kvlist, CNXK_RSS_TAG_AS_XOR, &parse_flag,\n+\t\t\t &rss_tag_as_xor);\n+\trte_kvargs_free(kvlist);\n+\n+null_devargs:\n+\tdev->scalar_ena = !!scalar_enable;\n+\tdev->nix.rss_tag_as_xor = !!rss_tag_as_xor;\n+\tdev->nix.max_sqb_count = sqb_count;\n+\tdev->nix.reta_sz = reta_sz;\n+\treturn 0;\n+\n+exit:\n+\treturn -EINVAL;\n+}\n+\n+RTE_PMD_REGISTER_PARAM_STRING(net_cnxk,\n+\t\t\t CNXK_RSS_RETA_SIZE \"=<64|128|256>\"\n+\t\t\t CNXK_SCL_ENABLE \"=1\"\n+\t\t\t CNXK_MAX_SQB_COUNT \"=<8-512>\"\n+\t\t\t CNXK_FLOW_PREALLOC_SIZE \"=<1-32>\"\n+\t\t\t CNXK_FLOW_MAX_PRIORITY \"=<1-32>\"\n+\t\t\t CNXK_SWITCH_HEADER_TYPE \"=<higig2|dsa|chlen90b>\"\n+\t\t\t CNXK_RSS_TAG_AS_XOR \"=1\");\ndiff --git a/drivers/net/cnxk/meson.build b/drivers/net/cnxk/meson.build\nindex 57dea5e..00c4722 100644\n--- a/drivers/net/cnxk/meson.build\n+++ b/drivers/net/cnxk/meson.build\n@@ -8,7 +8,8 @@ if not dpdk_conf.get('RTE_ARCH_64')\n \tsubdir_done()\n endif\n \n-sources = files('cnxk_ethdev.c')\n+sources = files('cnxk_ethdev.c',\n+\t\t'cnxk_ethdev_devargs.c')\n \n # CN9K\n sources += files('cn9k_ethdev.c')\n", "prefixes": [ "03/44" ] }