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GET /api/patches/88574/?format=api
{ "id": 88574, "url": "http://patches.dpdk.org/api/patches/88574/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210305133918.8005-48-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210305133918.8005-48-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210305133918.8005-48-ndabilpuram@marvell.com", "date": "2021-03-05T13:39:13", "name": "[47/52] common/cnxk: add sso hwgrp interface", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "9a04dac895c34e0d7ce13d091557ae16053f1806", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210305133918.8005-48-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 15508, "url": "http://patches.dpdk.org/api/series/15508/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=15508", "date": "2021-03-05T13:38:26", "name": "Add Marvell CNXK common driver", "version": 1, "mbox": "http://patches.dpdk.org/series/15508/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/88574/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/88574/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id F3CEBA0547;\n\tFri, 5 Mar 2021 14:47:59 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E743622A489;\n\tFri, 5 Mar 2021 14:41:54 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id D068222A3A3\n for <dev@dpdk.org>; Fri, 5 Mar 2021 14:41:52 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 125DerQc001873 for <dev@dpdk.org>; Fri, 5 Mar 2021 05:41:52 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 372s2umrt9-2\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Fri, 05 Mar 2021 05:41:52 -0800", "from SC-EXCH03.marvell.com (10.93.176.83) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Fri, 5 Mar 2021 05:41:50 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH03.marvell.com\n (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Fri, 5 Mar 2021 05:41:49 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Fri, 5 Mar 2021 05:41:49 -0800", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 645043F7041;\n Fri, 5 Mar 2021 05:41:47 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=ElO/yOIDpermh6kPKTz0E/YtBjxKM3TdmtMVUlnF6/0=;\n b=cwPfpMCwCVv8kjGjHJvNT2jFnggOL1g482rD+3Y4g5xThDY8R4GcpImb2seFLEtihwU7\n KEugyX/5ZNOOGuccIfVPK+Ao2WR2YhcDGSBifL+/4wE5rUBpwtGYrlMQRtyube+WrkFl\n H0AFcmbB9WUWd/8z4gelBT6N3/DzYhitB1SmkwM84RELdMedP+4bzifMhXPdh13aUxOm\n hDgiYPkjdNBlCBUfzojyUaIs3GsBgFPKb5My3qvHyIrLD9rJ/8my303m3V9oJ/H44tjw\n rGxtz/o9AfZCc6a9XENamKgpzXa1jSUnalkJzpc5DzT7jby/zL3aMmxt2cTRIdfH1iNi eQ==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>", "Date": "Fri, 5 Mar 2021 19:09:13 +0530", "Message-ID": "<20210305133918.8005-48-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210305133918.8005-1-ndabilpuram@marvell.com>", "References": "<20210305133918.8005-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-03-05_08:2021-03-03,\n 2021-03-05 signatures=0", "Subject": "[dpdk-dev] [PATCH 47/52] common/cnxk: add sso hwgrp interface", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd SSO HWGRP interface for configuring XAQ pool, setting priority\nand internal HW buffer limits for each HWGRP.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/common/cnxk/roc_sso.c | 110 ++++++++++++++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_sso.h | 21 ++++++++\n drivers/common/cnxk/version.map | 6 +++\n 3 files changed, 137 insertions(+)", "diff": "diff --git a/drivers/common/cnxk/roc_sso.c b/drivers/common/cnxk/roc_sso.c\nindex 52a7a6c..acb9be8 100644\n--- a/drivers/common/cnxk/roc_sso.c\n+++ b/drivers/common/cnxk/roc_sso.c\n@@ -174,6 +174,14 @@ roc_sso_hws_base_get(struct roc_sso *roc_sso, uint8_t hws)\n \treturn dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | hws << 12);\n }\n \n+uintptr_t\n+roc_sso_hwgrp_base_get(struct roc_sso *roc_sso, uint16_t hwgrp)\n+{\n+\tstruct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev;\n+\n+\treturn dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 | hwgrp << 12);\n+}\n+\n uint64_t\n roc_sso_ns_to_gw(struct roc_sso *roc_sso, uint64_t ns)\n {\n@@ -241,6 +249,108 @@ roc_sso_hws_unlink(struct roc_sso *roc_sso, uint8_t hws, uint16_t hwgrp[],\n }\n \n int\n+roc_sso_hwgrp_hws_link_status(struct roc_sso *roc_sso, uint8_t hws,\n+\t\t\t uint16_t hwgrp)\n+{\n+\tstruct sso *sso;\n+\n+\tsso = roc_sso_to_sso_priv(roc_sso);\n+\treturn plt_bitmap_get(sso->link_map[hws], hwgrp);\n+}\n+\n+int\n+roc_sso_hwgrp_qos_config(struct roc_sso *roc_sso, struct roc_sso_hwgrp_qos *qos,\n+\t\t\t uint8_t nb_qos, uint32_t nb_xaq)\n+{\n+\tstruct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev;\n+\tstruct sso_grp_qos_cfg *req;\n+\tint i, rc;\n+\n+\tfor (i = 0; i < nb_qos; i++) {\n+\t\tuint8_t xaq_prcnt = qos[i].xaq_prcnt;\n+\t\tuint8_t iaq_prcnt = qos[i].iaq_prcnt;\n+\t\tuint8_t taq_prcnt = qos[i].taq_prcnt;\n+\n+\t\treq = mbox_alloc_msg_sso_grp_qos_config(dev->mbox);\n+\t\tif (req == NULL) {\n+\t\t\trc = mbox_process(dev->mbox);\n+\t\t\tif (rc < 0)\n+\t\t\t\treturn rc;\n+\t\t\treq = mbox_alloc_msg_sso_grp_qos_config(dev->mbox);\n+\t\t\tif (req == NULL)\n+\t\t\t\treturn -ENOSPC;\n+\t\t}\n+\t\treq->grp = qos[i].hwgrp;\n+\t\treq->xaq_limit = (nb_xaq * (xaq_prcnt ? xaq_prcnt : 100)) / 100;\n+\t\treq->taq_thr = (SSO_HWGRP_IAQ_MAX_THR_MASK *\n+\t\t\t\t(iaq_prcnt ? iaq_prcnt : 100)) /\n+\t\t\t 100;\n+\t\treq->iaq_thr = (SSO_HWGRP_TAQ_MAX_THR_MASK *\n+\t\t\t\t(taq_prcnt ? taq_prcnt : 100)) /\n+\t\t\t 100;\n+\t}\n+\n+\treturn mbox_process(dev->mbox);\n+}\n+\n+int\n+roc_sso_hwgrp_alloc_xaq(struct roc_sso *roc_sso, uint32_t npa_aura_id,\n+\t\t\tuint16_t hwgrps)\n+{\n+\tstruct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev;\n+\tstruct sso_hw_setconfig *req;\n+\tint rc = -ENOSPC;\n+\n+\treq = mbox_alloc_msg_sso_hw_setconfig(dev->mbox);\n+\tif (req == NULL)\n+\t\treturn rc;\n+\treq->npa_pf_func = idev_npa_pffunc_get();\n+\treq->npa_aura_id = npa_aura_id;\n+\treq->hwgrps = hwgrps;\n+\n+\treturn mbox_process(dev->mbox);\n+}\n+\n+int\n+roc_sso_hwgrp_release_xaq(struct roc_sso *roc_sso, uint16_t hwgrps)\n+{\n+\tstruct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev;\n+\tstruct sso_hw_xaq_release *req;\n+\n+\treq = mbox_alloc_msg_sso_hw_release_xaq_aura(dev->mbox);\n+\tif (req == NULL)\n+\t\treturn -EINVAL;\n+\treq->hwgrps = hwgrps;\n+\n+\treturn mbox_process(dev->mbox);\n+}\n+\n+int\n+roc_sso_hwgrp_set_priority(struct roc_sso *roc_sso, uint16_t hwgrp,\n+\t\t\t uint8_t weight, uint8_t affinity, uint8_t priority)\n+{\n+\tstruct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev;\n+\tstruct sso_grp_priority *req;\n+\tint rc = -ENOSPC;\n+\n+\treq = mbox_alloc_msg_sso_grp_set_priority(dev->mbox);\n+\tif (req == NULL)\n+\t\treturn rc;\n+\treq->grp = hwgrp;\n+\treq->weight = weight;\n+\treq->affinity = affinity;\n+\treq->priority = priority;\n+\n+\trc = mbox_process(dev->mbox);\n+\tif (rc < 0)\n+\t\treturn rc;\n+\tplt_sso_dbg(\"HWGRP %d weight %d affinity %d priority %d\", hwgrp, weight,\n+\t\t affinity, priority);\n+\n+\treturn 0;\n+}\n+\n+int\n roc_sso_rsrc_init(struct roc_sso *roc_sso, uint8_t nb_hws, uint16_t nb_hwgrp)\n {\n \tstruct sso_lf_alloc_rsp *rsp_hwgrp;\ndiff --git a/drivers/common/cnxk/roc_sso.h b/drivers/common/cnxk/roc_sso.h\nindex c4f5c40..fa5f4ea 100644\n--- a/drivers/common/cnxk/roc_sso.h\n+++ b/drivers/common/cnxk/roc_sso.h\n@@ -5,6 +5,13 @@\n #ifndef _ROC_SSO_H_\n #define _ROC_SSO_H_\n \n+struct roc_sso_hwgrp_qos {\n+\tuint16_t hwgrp;\n+\tuint8_t xaq_prcnt;\n+\tuint8_t iaq_prcnt;\n+\tuint8_t taq_prcnt;\n+};\n+\n struct roc_sso {\n \tstruct plt_pci_device *pci_dev;\n \t/* Public data. */\n@@ -30,11 +37,25 @@ int __roc_api roc_sso_dev_fini(struct roc_sso *roc_sso);\n int __roc_api roc_sso_rsrc_init(struct roc_sso *roc_sso, uint8_t nb_hws,\n \t\t\t\tuint16_t nb_hwgrp);\n void __roc_api roc_sso_rsrc_fini(struct roc_sso *roc_sso);\n+int __roc_api roc_sso_hwgrp_qos_config(struct roc_sso *roc_sso,\n+\t\t\t\t struct roc_sso_hwgrp_qos *qos,\n+\t\t\t\t uint8_t nb_qos, uint32_t nb_xaq);\n+int __roc_api roc_sso_hwgrp_alloc_xaq(struct roc_sso *roc_sso,\n+\t\t\t\t uint32_t npa_aura_id, uint16_t hwgrps);\n+int __roc_api roc_sso_hwgrp_release_xaq(struct roc_sso *roc_sso,\n+\t\t\t\t\tuint16_t hwgrps);\n+int __roc_api roc_sso_hwgrp_set_priority(struct roc_sso *roc_sso,\n+\t\t\t\t\t uint16_t hwgrp, uint8_t weight,\n+\t\t\t\t\t uint8_t affinity, uint8_t priority);\n uint64_t __roc_api roc_sso_ns_to_gw(struct roc_sso *roc_sso, uint64_t ns);\n int __roc_api roc_sso_hws_link(struct roc_sso *roc_sso, uint8_t hws,\n \t\t\t uint16_t hwgrp[], uint16_t nb_hwgrp);\n int __roc_api roc_sso_hws_unlink(struct roc_sso *roc_sso, uint8_t hws,\n \t\t\t\t uint16_t hwgrp[], uint16_t nb_hwgrp);\n+int __roc_api roc_sso_hwgrp_hws_link_status(struct roc_sso *roc_sso,\n+\t\t\t\t\t uint8_t hws, uint16_t hwgrp);\n uintptr_t __roc_api roc_sso_hws_base_get(struct roc_sso *roc_sso, uint8_t hws);\n+uintptr_t __roc_api roc_sso_hwgrp_base_get(struct roc_sso *roc_sso,\n+\t\t\t\t\t uint16_t hwgrp);\n \n #endif /* _ROC_SSOW_H_ */\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 5675a39..7dde169 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -174,6 +174,12 @@ INTERNAL {\n \troc_npc_profile_name_get;\n \troc_sso_dev_fini;\n \troc_sso_dev_init;\n+\troc_sso_hwgrp_alloc_xaq;\n+\troc_sso_hwgrp_base_get;\n+\troc_sso_hwgrp_hws_link_status;\n+\troc_sso_hwgrp_qos_config;\n+\troc_sso_hwgrp_release_xaq;\n+\troc_sso_hwgrp_set_priority;\n \troc_sso_hws_base_get;\n \troc_sso_hws_link;\n \troc_sso_hws_unlink;\n", "prefixes": [ "47/52" ] }