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GET /api/patches/88553/?format=api
{ "id": 88553, "url": "http://patches.dpdk.org/api/patches/88553/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210305133918.8005-27-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210305133918.8005-27-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210305133918.8005-27-ndabilpuram@marvell.com", "date": "2021-03-05T13:38:52", "name": "[26/52] common/cnxk: add nix stats support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "0c92a47df2ff90bebdd7d2d824ccb129b7376ec4", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210305133918.8005-27-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 15508, "url": "http://patches.dpdk.org/api/series/15508/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=15508", "date": "2021-03-05T13:38:26", "name": "Add Marvell CNXK common driver", "version": 1, "mbox": "http://patches.dpdk.org/series/15508/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/88553/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/88553/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7B079A0547;\n\tFri, 5 Mar 2021 14:44:19 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3C44622A3E8;\n\tFri, 5 Mar 2021 14:40:52 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 85C7222A378\n for <dev@dpdk.org>; Fri, 5 Mar 2021 14:40:49 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 125DelHX001661 for <dev@dpdk.org>; Fri, 5 Mar 2021 05:40:48 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com with ESMTP id 372s2umrp7-4\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Fri, 05 Mar 2021 05:40:48 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Fri, 5 Mar 2021 05:40:46 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Fri, 5 Mar 2021 05:40:46 -0800", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 562DB3F7043;\n Fri, 5 Mar 2021 05:40:44 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=qDKKZlWc8gZEpfe2mZy06TMK23RyZyht2JS3fySNPh0=;\n b=iFjEwfQp7yeLpsTd9kk4MfZxz5z/gDcAsEANfxxqNIIxh+b5IWYSKv6u+7cIHoSnMWpF\n u1RjV8kezp5xkXM8e3QhFiAjWojwexQn70uHSUNhrGfJiIYOh57JeR8Szs/74IeANCT7\n Rb9pw19UJWvfzyYENi0pxoPoR1cgNH7klqYb0gHpsEML7qQyunX88jbwjdIOjMSL3u6d\n aQBIq4COVT34qxm1a4K6TwDESSSCaR0xddRbeAmi4bAjbV6wfLSI+SeD3UheMjprs4OE\n IXlwKi/JfFbF6j+3/VLNUFWIuGNu2dMUowjso5Pv/+F2XtWu0JqZb2kGI28ZdPIic7vP 6w==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>", "Date": "Fri, 5 Mar 2021 19:08:52 +0530", "Message-ID": "<20210305133918.8005-27-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210305133918.8005-1-ndabilpuram@marvell.com>", "References": "<20210305133918.8005-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-03-05_08:2021-03-03,\n 2021-03-05 signatures=0", "Subject": "[dpdk-dev] [PATCH 26/52] common/cnxk: add nix stats support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nAdd API to provide Rx and Tx stats for a given NIX.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\n---\n drivers/common/cnxk/meson.build | 1 +\n drivers/common/cnxk/roc_nix.h | 53 ++++++++\n drivers/common/cnxk/roc_nix_stats.c | 239 ++++++++++++++++++++++++++++++++++++\n drivers/common/cnxk/version.map | 4 +\n 4 files changed, 297 insertions(+)\n create mode 100644 drivers/common/cnxk/roc_nix_stats.c", "diff": "diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build\nindex 65dadd9..199c6d4 100644\n--- a/drivers/common/cnxk/meson.build\n+++ b/drivers/common/cnxk/meson.build\n@@ -24,6 +24,7 @@ sources = files('roc_dev.c',\n \t\t'roc_nix_ptp.c',\n \t\t'roc_nix_queue.c',\n \t\t'roc_nix_rss.c',\n+\t\t'roc_nix_stats.c',\n \t\t'roc_npa.c',\n \t\t'roc_npa_debug.c',\n \t\t'roc_npa_irq.c',\ndiff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex 90a5ac9..ee9e78b 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -42,6 +42,49 @@ enum roc_nix_sq_max_sqe_sz {\n #define ROC_NIX_VWQE_MAX_SIZE_LOG2 11\n #define ROC_NIX_VWQE_MIN_SIZE_LOG2 2\n \n+struct roc_nix_stats {\n+\t/* Rx */\n+\tuint64_t rx_octs;\n+\tuint64_t rx_ucast;\n+\tuint64_t rx_bcast;\n+\tuint64_t rx_mcast;\n+\tuint64_t rx_drop;\n+\tuint64_t rx_drop_octs;\n+\tuint64_t rx_fcs;\n+\tuint64_t rx_err;\n+\tuint64_t rx_drop_bcast;\n+\tuint64_t rx_drop_mcast;\n+\tuint64_t rx_drop_l3_bcast;\n+\tuint64_t rx_drop_l3_mcast;\n+\t/* Tx */\n+\tuint64_t tx_ucast;\n+\tuint64_t tx_bcast;\n+\tuint64_t tx_mcast;\n+\tuint64_t tx_drop;\n+\tuint64_t tx_octs;\n+};\n+\n+struct roc_nix_stats_queue {\n+\tPLT_STD_C11\n+\tunion {\n+\t\tstruct {\n+\t\t\t/* Rx */\n+\t\t\tuint64_t rx_pkts;\n+\t\t\tuint64_t rx_octs;\n+\t\t\tuint64_t rx_drop_pkts;\n+\t\t\tuint64_t rx_drop_octs;\n+\t\t\tuint64_t rx_error_pkts;\n+\t\t};\n+\t\tstruct {\n+\t\t\t/* Tx */\n+\t\t\tuint64_t tx_pkts;\n+\t\t\tuint64_t tx_octs;\n+\t\t\tuint64_t tx_drop_pkts;\n+\t\t\tuint64_t tx_drop_octs;\n+\t\t};\n+\t};\n+};\n+\n struct roc_nix_rq {\n \t/* Input parameters */\n \tuint16_t qid;\n@@ -232,6 +275,16 @@ int __roc_api roc_nix_rss_flowkey_set(struct roc_nix *roc_nix, uint8_t *alg_idx,\n int __roc_api roc_nix_rss_default_setup(struct roc_nix *roc_nix,\n \t\t\t\t\tuint32_t flowkey);\n \n+/* Stats */\n+int __roc_api roc_nix_stats_get(struct roc_nix *roc_nix,\n+\t\t\t\tstruct roc_nix_stats *stats);\n+int __roc_api roc_nix_stats_reset(struct roc_nix *roc_nix);\n+int __roc_api roc_nix_stats_queue_get(struct roc_nix *roc_nix, uint16_t qid,\n+\t\t\t\t bool is_rx,\n+\t\t\t\t struct roc_nix_stats_queue *qstats);\n+int __roc_api roc_nix_stats_queue_reset(struct roc_nix *roc_nix, uint16_t qid,\n+\t\t\t\t\tbool is_rx);\n+\n /* Queue */\n int __roc_api roc_nix_rq_init(struct roc_nix *roc_nix, struct roc_nix_rq *rq,\n \t\t\t bool ena);\ndiff --git a/drivers/common/cnxk/roc_nix_stats.c b/drivers/common/cnxk/roc_nix_stats.c\nnew file mode 100644\nindex 0000000..dce496c\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_nix_stats.c\n@@ -0,0 +1,239 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2020 Marvell.\n+ */\n+\n+#include <inttypes.h>\n+\n+#include \"roc_api.h\"\n+#include \"roc_priv.h\"\n+\n+#define NIX_RX_STATS(val) plt_read64(nix->base + NIX_LF_RX_STATX(val))\n+#define NIX_TX_STATS(val) plt_read64(nix->base + NIX_LF_TX_STATX(val))\n+\n+int\n+roc_nix_stats_get(struct roc_nix *roc_nix, struct roc_nix_stats *stats)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\n+\tif (stats == NULL)\n+\t\treturn NIX_ERR_PARAM;\n+\n+\tstats->rx_octs = NIX_RX_STATS(NIX_STAT_LF_RX_RX_OCTS);\n+\tstats->rx_ucast = NIX_RX_STATS(NIX_STAT_LF_RX_RX_UCAST);\n+\tstats->rx_bcast = NIX_RX_STATS(NIX_STAT_LF_RX_RX_BCAST);\n+\tstats->rx_mcast = NIX_RX_STATS(NIX_STAT_LF_RX_RX_MCAST);\n+\tstats->rx_drop = NIX_RX_STATS(NIX_STAT_LF_RX_RX_DROP);\n+\tstats->rx_drop_octs = NIX_RX_STATS(NIX_STAT_LF_RX_RX_DROP_OCTS);\n+\tstats->rx_fcs = NIX_RX_STATS(NIX_STAT_LF_RX_RX_FCS);\n+\tstats->rx_err = NIX_RX_STATS(NIX_STAT_LF_RX_RX_ERR);\n+\tstats->rx_drop_bcast = NIX_RX_STATS(NIX_STAT_LF_RX_RX_DRP_BCAST);\n+\tstats->rx_drop_mcast = NIX_RX_STATS(NIX_STAT_LF_RX_RX_DRP_MCAST);\n+\tstats->rx_drop_l3_bcast = NIX_RX_STATS(NIX_STAT_LF_RX_RX_DRP_L3BCAST);\n+\tstats->rx_drop_l3_mcast = NIX_RX_STATS(NIX_STAT_LF_RX_RX_DRP_L3MCAST);\n+\n+\tstats->tx_ucast = NIX_TX_STATS(NIX_STAT_LF_TX_TX_UCAST);\n+\tstats->tx_bcast = NIX_TX_STATS(NIX_STAT_LF_TX_TX_BCAST);\n+\tstats->tx_mcast = NIX_TX_STATS(NIX_STAT_LF_TX_TX_MCAST);\n+\tstats->tx_drop = NIX_TX_STATS(NIX_STAT_LF_TX_TX_DROP);\n+\tstats->tx_octs = NIX_TX_STATS(NIX_STAT_LF_TX_TX_OCTS);\n+\treturn 0;\n+}\n+\n+int\n+roc_nix_stats_reset(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\n+\tif (mbox_alloc_msg_nix_stats_rst(mbox) == NULL)\n+\t\treturn -ENOMEM;\n+\n+\treturn mbox_process(mbox);\n+}\n+\n+static int\n+queue_is_valid(struct nix *nix, uint16_t qid, bool is_rx)\n+{\n+\tuint16_t nb_queues;\n+\n+\tif (is_rx)\n+\t\tnb_queues = nix->nb_rx_queues;\n+\telse\n+\t\tnb_queues = nix->nb_tx_queues;\n+\n+\tif (qid >= nb_queues)\n+\t\treturn NIX_ERR_QUEUE_INVALID_RANGE;\n+\n+\treturn 0;\n+}\n+\n+static uint64_t\n+qstat_read(struct nix *nix, uint16_t qid, uint32_t off)\n+{\n+\tuint64_t reg, val;\n+\tint64_t *addr;\n+\n+\taddr = (int64_t *)(nix->base + off);\n+\treg = (((uint64_t)qid) << 32);\n+\tval = roc_atomic64_add_nosync(reg, addr);\n+\tif (val & BIT_ULL(NIX_CQ_OP_STAT_OP_ERR))\n+\t\tval = 0;\n+\treturn val;\n+}\n+\n+static void\n+nix_stat_rx_queue_get(struct nix *nix, uint16_t qid,\n+\t\t struct roc_nix_stats_queue *qstats)\n+{\n+\tqstats->rx_pkts = qstat_read(nix, qid, NIX_LF_RQ_OP_PKTS);\n+\tqstats->rx_octs = qstat_read(nix, qid, NIX_LF_RQ_OP_OCTS);\n+\tqstats->rx_drop_pkts = qstat_read(nix, qid, NIX_LF_RQ_OP_DROP_PKTS);\n+\tqstats->rx_drop_octs = qstat_read(nix, qid, NIX_LF_RQ_OP_DROP_OCTS);\n+\tqstats->rx_error_pkts = qstat_read(nix, qid, NIX_LF_RQ_OP_RE_PKTS);\n+}\n+\n+static void\n+nix_stat_tx_queue_get(struct nix *nix, uint16_t qid,\n+\t\t struct roc_nix_stats_queue *qstats)\n+{\n+\tqstats->tx_pkts = qstat_read(nix, qid, NIX_LF_SQ_OP_PKTS);\n+\tqstats->tx_octs = qstat_read(nix, qid, NIX_LF_SQ_OP_OCTS);\n+\tqstats->tx_drop_pkts = qstat_read(nix, qid, NIX_LF_SQ_OP_DROP_PKTS);\n+\tqstats->tx_drop_octs = qstat_read(nix, qid, NIX_LF_SQ_OP_DROP_OCTS);\n+}\n+\n+static int\n+nix_stat_rx_queue_reset(struct nix *nix, uint16_t qid)\n+{\n+\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tint rc;\n+\n+\tif (roc_model_is_cn9k()) {\n+\t\tstruct nix_aq_enq_req *aq;\n+\n+\t\taq = mbox_alloc_msg_nix_aq_enq(mbox);\n+\t\taq->qidx = qid;\n+\t\taq->ctype = NIX_AQ_CTYPE_RQ;\n+\t\taq->op = NIX_AQ_INSTOP_WRITE;\n+\n+\t\taq->rq.octs = 0;\n+\t\taq->rq.pkts = 0;\n+\t\taq->rq.drop_octs = 0;\n+\t\taq->rq.drop_pkts = 0;\n+\t\taq->rq.re_pkts = 0;\n+\n+\t\taq->rq_mask.octs = ~(aq->rq_mask.octs);\n+\t\taq->rq_mask.pkts = ~(aq->rq_mask.pkts);\n+\t\taq->rq_mask.drop_octs = ~(aq->rq_mask.drop_octs);\n+\t\taq->rq_mask.drop_pkts = ~(aq->rq_mask.drop_pkts);\n+\t\taq->rq_mask.re_pkts = ~(aq->rq_mask.re_pkts);\n+\t} else {\n+\t\tstruct nix_cn10k_aq_enq_req *aq;\n+\n+\t\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n+\t\taq->qidx = qid;\n+\t\taq->ctype = NIX_AQ_CTYPE_RQ;\n+\t\taq->op = NIX_AQ_INSTOP_WRITE;\n+\n+\t\taq->rq.octs = 0;\n+\t\taq->rq.pkts = 0;\n+\t\taq->rq.drop_octs = 0;\n+\t\taq->rq.drop_pkts = 0;\n+\t\taq->rq.re_pkts = 0;\n+\n+\t\taq->rq_mask.octs = ~(aq->rq_mask.octs);\n+\t\taq->rq_mask.pkts = ~(aq->rq_mask.pkts);\n+\t\taq->rq_mask.drop_octs = ~(aq->rq_mask.drop_octs);\n+\t\taq->rq_mask.drop_pkts = ~(aq->rq_mask.drop_pkts);\n+\t\taq->rq_mask.re_pkts = ~(aq->rq_mask.re_pkts);\n+\t}\n+\n+\trc = mbox_process(mbox);\n+\treturn rc ? NIX_ERR_AQ_WRITE_FAILED : 0;\n+}\n+\n+static int\n+nix_stat_tx_queue_reset(struct nix *nix, uint16_t qid)\n+{\n+\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tint rc;\n+\n+\tif (roc_model_is_cn9k()) {\n+\t\tstruct nix_aq_enq_req *aq;\n+\n+\t\taq = mbox_alloc_msg_nix_aq_enq(mbox);\n+\t\taq->qidx = qid;\n+\t\taq->ctype = NIX_AQ_CTYPE_SQ;\n+\t\taq->op = NIX_AQ_INSTOP_WRITE;\n+\t\taq->sq.octs = 0;\n+\t\taq->sq.pkts = 0;\n+\t\taq->sq.drop_octs = 0;\n+\t\taq->sq.drop_pkts = 0;\n+\n+\t\taq->sq_mask.octs = ~(aq->sq_mask.octs);\n+\t\taq->sq_mask.pkts = ~(aq->sq_mask.pkts);\n+\t\taq->sq_mask.drop_octs = ~(aq->sq_mask.drop_octs);\n+\t\taq->sq_mask.drop_pkts = ~(aq->sq_mask.drop_pkts);\n+\t} else {\n+\t\tstruct nix_cn10k_aq_enq_req *aq;\n+\n+\t\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n+\t\taq->qidx = qid;\n+\t\taq->ctype = NIX_AQ_CTYPE_SQ;\n+\t\taq->op = NIX_AQ_INSTOP_WRITE;\n+\t\taq->sq.octs = 0;\n+\t\taq->sq.pkts = 0;\n+\t\taq->sq.drop_octs = 0;\n+\t\taq->sq.drop_pkts = 0;\n+\n+\t\taq->sq_mask.octs = ~(aq->sq_mask.octs);\n+\t\taq->sq_mask.pkts = ~(aq->sq_mask.pkts);\n+\t\taq->sq_mask.drop_octs = ~(aq->sq_mask.drop_octs);\n+\t\taq->sq_mask.drop_pkts = ~(aq->sq_mask.drop_pkts);\n+\t}\n+\n+\trc = mbox_process(mbox);\n+\treturn rc ? NIX_ERR_AQ_WRITE_FAILED : 0;\n+}\n+\n+int\n+roc_nix_stats_queue_get(struct roc_nix *roc_nix, uint16_t qid, bool is_rx,\n+\t\t\tstruct roc_nix_stats_queue *qstats)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tint rc;\n+\n+\tif (qstats == NULL)\n+\t\treturn NIX_ERR_PARAM;\n+\n+\trc = queue_is_valid(nix, qid, is_rx);\n+\tif (rc)\n+\t\tgoto fail;\n+\n+\tif (is_rx)\n+\t\tnix_stat_rx_queue_get(nix, qid, qstats);\n+\telse\n+\t\tnix_stat_tx_queue_get(nix, qid, qstats);\n+\n+fail:\n+\treturn rc;\n+}\n+\n+int\n+roc_nix_stats_queue_reset(struct roc_nix *roc_nix, uint16_t qid, bool is_rx)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tint rc;\n+\n+\trc = queue_is_valid(nix, qid, is_rx);\n+\tif (rc)\n+\t\tgoto fail;\n+\n+\tif (is_rx)\n+\t\trc = nix_stat_rx_queue_reset(nix, qid);\n+\telse\n+\t\trc = nix_stat_tx_queue_reset(nix, qid);\n+\n+fail:\n+\treturn rc;\n+}\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex bd3b834..8c6df6d 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -80,6 +80,10 @@ INTERNAL {\n \troc_nix_rx_queue_intr_enable;\n \troc_nix_sq_fini;\n \troc_nix_sq_init;\n+\troc_nix_stats_get;\n+\troc_nix_stats_queue_get;\n+\troc_nix_stats_queue_reset;\n+\troc_nix_stats_reset;\n \troc_nix_unregister_cq_irqs;\n \troc_nix_unregister_queue_irqs;\n \troc_npa_aura_limit_modify;\n", "prefixes": [ "26/52" ] }