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GET /api/patches/88540/?format=api
{ "id": 88540, "url": "http://patches.dpdk.org/api/patches/88540/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210305133918.8005-14-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210305133918.8005-14-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210305133918.8005-14-ndabilpuram@marvell.com", "date": "2021-03-05T13:38:39", "name": "[13/52] common/cnxk: add npa bulk alloc/free support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "b56f2803266f8486cdd2755efb0653b5dd2b8858", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210305133918.8005-14-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 15508, "url": "http://patches.dpdk.org/api/series/15508/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=15508", "date": "2021-03-05T13:38:26", "name": "Add Marvell CNXK common driver", "version": 1, "mbox": "http://patches.dpdk.org/series/15508/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/88540/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/88540/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 6A705A0547;\n\tFri, 5 Mar 2021 14:42:05 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E7DEF22A39C;\n\tFri, 5 Mar 2021 14:40:12 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id A0E2222A39C\n for <dev@dpdk.org>; Fri, 5 Mar 2021 14:40:11 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 125De000008966 for <dev@dpdk.org>; Fri, 5 Mar 2021 05:40:11 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 370p7p0dc3-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Fri, 05 Mar 2021 05:40:11 -0800", "from SC-EXCH03.marvell.com (10.93.176.83) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Fri, 5 Mar 2021 05:40:09 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH03.marvell.com\n (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Fri, 5 Mar 2021 05:40:08 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Fri, 5 Mar 2021 05:40:08 -0800", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id EFDA73F7040;\n Fri, 5 Mar 2021 05:40:05 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=mewvWGUtcu/Gz6e6Y2BNGxroPUHlSY+mAp2IJss/qkk=;\n b=F5SicNKLYKaNMACZffls92Sh+Fe3xnPrz/jgUCPJ5jvbNoZM9o5G+h/cnUeSrulOnuDf\n JCLR/iE+tvMG4X7HwGCQHqVkj2yoMAIR4Utiyr/t3S6q7zV7J0cnLj3m2FsdegtGfqui\n 0AQ+WN23+tyMe1Njg52U8Bk19uC0QSePRzxtTe4hOiSI2VncCZQeurhcfboxyeGLGpxe\n pboQeI94XXEVWNzvoRH90rRN69YU9calWzUZrZye+/E0gBsGPr7/b2hZvlBb8M+AXszk\n 5AUBYBuPWgr/a/8EUf/4PlhRIcnMHMF37SSKNMlVedy0b0qaVLb+S7gBpdU18G+OWLYz +g==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>", "Date": "Fri, 5 Mar 2021 19:08:39 +0530", "Message-ID": "<20210305133918.8005-14-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210305133918.8005-1-ndabilpuram@marvell.com>", "References": "<20210305133918.8005-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-03-05_08:2021-03-03,\n 2021-03-05 signatures=0", "Subject": "[dpdk-dev] [PATCH 13/52] common/cnxk: add npa bulk alloc/free\n support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Ashwin Sekhar T K <asekhar@marvell.com>\n\nAdd APIs to alloc/free in bulk from NPA pool.\n\nSigned-off-by: Ashwin Sekhar T K <asekhar@marvell.com>\n---\n drivers/common/cnxk/roc_npa.h | 229 ++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 229 insertions(+)", "diff": "diff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h\nindex 0dffede..ed63718 100644\n--- a/drivers/common/cnxk/roc_npa.h\n+++ b/drivers/common/cnxk/roc_npa.h\n@@ -8,6 +8,11 @@\n #define ROC_AURA_ID_MASK (BIT_ULL(16) - 1)\n #define ROC_AURA_OP_LIMIT_MASK (BIT_ULL(36) - 1)\n \n+/* 16 CASP instructions can be outstanding in CN9k, but we use only 15\n+ * outstanding CASPs as we run out of registers.\n+ */\n+#define ROC_CN9K_NPA_BULK_ALLOC_MAX_PTRS 30\n+\n /*\n * Generate 64bit handle to have optimized alloc and free aura operation.\n * 0 - ROC_AURA_ID_MASK for storing the aura_id.\n@@ -141,6 +146,230 @@ roc_npa_aura_op_available(uint64_t aura_handle)\n \t\treturn reg & 0xFFFFFFFFF;\n }\n \n+static inline void\n+roc_npa_aura_op_bulk_free(uint64_t aura_handle, uint64_t const *buf,\n+\t\t\t unsigned int num, const int fabs)\n+{\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < num; i++) {\n+\t\tconst uint64_t inbuf = buf[i];\n+\n+\t\troc_npa_aura_op_free(aura_handle, fabs, inbuf);\n+\t}\n+}\n+\n+static inline unsigned int\n+roc_npa_aura_bulk_alloc(uint64_t aura_handle, uint64_t *buf, unsigned int num,\n+\t\t\tconst int drop)\n+{\n+#if defined(__aarch64__)\n+\tuint64_t wdata = roc_npa_aura_handle_to_aura(aura_handle);\n+\tunsigned int i, count;\n+\tuint64_t addr;\n+\n+\tif (drop)\n+\t\twdata |= BIT_ULL(63); /* DROP */\n+\n+\taddr = roc_npa_aura_handle_to_base(aura_handle) +\n+\t NPA_LF_AURA_OP_ALLOCX(0);\n+\n+\tswitch (num) {\n+\tcase 30:\n+\t\tasm volatile(\n+\t\t\t\".cpu generic+lse\\n\"\n+\t\t\t\"mov v18.d[0], %[dst]\\n\"\n+\t\t\t\"mov v18.d[1], %[loc]\\n\"\n+\t\t\t\"mov v19.d[0], %[wdata]\\n\"\n+\t\t\t\"mov v19.d[1], x30\\n\"\n+\t\t\t\"mov v20.d[0], x24\\n\"\n+\t\t\t\"mov v20.d[1], x25\\n\"\n+\t\t\t\"mov v21.d[0], x26\\n\"\n+\t\t\t\"mov v21.d[1], x27\\n\"\n+\t\t\t\"mov v22.d[0], x28\\n\"\n+\t\t\t\"mov v22.d[1], x29\\n\"\n+\t\t\t\"mov x28, v19.d[0]\\n\"\n+\t\t\t\"mov x29, v19.d[0]\\n\"\n+\t\t\t\"mov x30, v18.d[1]\\n\"\n+\t\t\t\"casp x0, x1, x28, x29, [x30]\\n\"\n+\t\t\t\"casp x2, x3, x28, x29, [x30]\\n\"\n+\t\t\t\"casp x4, x5, x28, x29, [x30]\\n\"\n+\t\t\t\"casp x6, x7, x28, x29, [x30]\\n\"\n+\t\t\t\"casp x8, x9, x28, x29, [x30]\\n\"\n+\t\t\t\"casp x10, x11, x28, x29, [x30]\\n\"\n+\t\t\t\"casp x12, x13, x28, x29, [x30]\\n\"\n+\t\t\t\"casp x14, x15, x28, x29, [x30]\\n\"\n+\t\t\t\"casp x16, x17, x28, x29, [x30]\\n\"\n+\t\t\t\"casp x18, x19, x28, x29, [x30]\\n\"\n+\t\t\t\"casp x20, x21, x28, x29, [x30]\\n\"\n+\t\t\t\"casp x22, x23, x28, x29, [x30]\\n\"\n+\t\t\t\"casp x24, x25, x28, x29, [x30]\\n\"\n+\t\t\t\"casp x26, x27, x28, x29, [x30]\\n\"\n+\t\t\t\"casp x28, x29, x28, x29, [x30]\\n\"\n+\t\t\t\"mov x30, v18.d[0]\\n\"\n+\t\t\t\"stp x0, x1, [x30]\\n\"\n+\t\t\t\"stp x2, x3, [x30, #16]\\n\"\n+\t\t\t\"stp x4, x5, [x30, #32]\\n\"\n+\t\t\t\"stp x6, x7, [x30, #48]\\n\"\n+\t\t\t\"stp x8, x9, [x30, #64]\\n\"\n+\t\t\t\"stp x10, x11, [x30, #80]\\n\"\n+\t\t\t\"stp x12, x13, [x30, #96]\\n\"\n+\t\t\t\"stp x14, x15, [x30, #112]\\n\"\n+\t\t\t\"stp x16, x17, [x30, #128]\\n\"\n+\t\t\t\"stp x18, x19, [x30, #144]\\n\"\n+\t\t\t\"stp x20, x21, [x30, #160]\\n\"\n+\t\t\t\"stp x22, x23, [x30, #176]\\n\"\n+\t\t\t\"stp x24, x25, [x30, #192]\\n\"\n+\t\t\t\"stp x26, x27, [x30, #208]\\n\"\n+\t\t\t\"stp x28, x29, [x30, #224]\\n\"\n+\t\t\t\"mov %[dst], v18.d[0]\\n\"\n+\t\t\t\"mov %[loc], v18.d[1]\\n\"\n+\t\t\t\"mov %[wdata], v19.d[0]\\n\"\n+\t\t\t\"mov x30, v19.d[1]\\n\"\n+\t\t\t\"mov x24, v20.d[0]\\n\"\n+\t\t\t\"mov x25, v20.d[1]\\n\"\n+\t\t\t\"mov x26, v21.d[0]\\n\"\n+\t\t\t\"mov x27, v21.d[1]\\n\"\n+\t\t\t\"mov x28, v22.d[0]\\n\"\n+\t\t\t\"mov x29, v22.d[1]\\n\"\n+\t\t\t:\n+\t\t\t: [wdata] \"r\"(wdata), [loc] \"r\"(addr), [dst] \"r\"(buf)\n+\t\t\t: \"memory\", \"x0\", \"x1\", \"x2\", \"x3\", \"x4\", \"x5\", \"x6\",\n+\t\t\t \"x7\", \"x8\", \"x9\", \"x10\", \"x11\", \"x12\", \"x13\", \"x14\",\n+\t\t\t \"x15\", \"x16\", \"x17\", \"x18\", \"x19\", \"x20\", \"x21\",\n+\t\t\t \"x22\", \"x23\", \"v18\", \"v19\", \"v20\", \"v21\", \"v22\");\n+\t\tbreak;\n+\tcase 16:\n+\t\tasm volatile(\n+\t\t\t\".cpu generic+lse\\n\"\n+\t\t\t\"mov x16, %[wdata]\\n\"\n+\t\t\t\"mov x17, %[wdata]\\n\"\n+\t\t\t\"casp x0, x1, x16, x17, [%[loc]]\\n\"\n+\t\t\t\"casp x2, x3, x16, x17, [%[loc]]\\n\"\n+\t\t\t\"casp x4, x5, x16, x17, [%[loc]]\\n\"\n+\t\t\t\"casp x6, x7, x16, x17, [%[loc]]\\n\"\n+\t\t\t\"casp x8, x9, x16, x17, [%[loc]]\\n\"\n+\t\t\t\"casp x10, x11, x16, x17, [%[loc]]\\n\"\n+\t\t\t\"casp x12, x13, x16, x17, [%[loc]]\\n\"\n+\t\t\t\"casp x14, x15, x16, x17, [%[loc]]\\n\"\n+\t\t\t\"stp x0, x1, [%[dst]]\\n\"\n+\t\t\t\"stp x2, x3, [%[dst], #16]\\n\"\n+\t\t\t\"stp x4, x5, [%[dst], #32]\\n\"\n+\t\t\t\"stp x6, x7, [%[dst], #48]\\n\"\n+\t\t\t\"stp x8, x9, [%[dst], #64]\\n\"\n+\t\t\t\"stp x10, x11, [%[dst], #80]\\n\"\n+\t\t\t\"stp x12, x13, [%[dst], #96]\\n\"\n+\t\t\t\"stp x14, x15, [%[dst], #112]\\n\"\n+\t\t\t:\n+\t\t\t: [wdata] \"r\" (wdata), [dst] \"r\" (buf), [loc] \"r\" (addr)\n+\t\t\t: \"memory\", \"x0\", \"x1\", \"x2\", \"x3\", \"x4\", \"x5\", \"x6\",\n+\t\t\t \"x7\", \"x8\", \"x9\", \"x10\", \"x11\", \"x12\", \"x13\", \"x14\",\n+\t\t\t \"x15\", \"x16\", \"x17\"\n+\t\t);\n+\t\tbreak;\n+\tcase 8:\n+\t\tasm volatile(\n+\t\t\t\".cpu generic+lse\\n\"\n+\t\t\t\"mov x16, %[wdata]\\n\"\n+\t\t\t\"mov x17, %[wdata]\\n\"\n+\t\t\t\"casp x0, x1, x16, x17, [%[loc]]\\n\"\n+\t\t\t\"casp x2, x3, x16, x17, [%[loc]]\\n\"\n+\t\t\t\"casp x4, x5, x16, x17, [%[loc]]\\n\"\n+\t\t\t\"casp x6, x7, x16, x17, [%[loc]]\\n\"\n+\t\t\t\"stp x0, x1, [%[dst]]\\n\"\n+\t\t\t\"stp x2, x3, [%[dst], #16]\\n\"\n+\t\t\t\"stp x4, x5, [%[dst], #32]\\n\"\n+\t\t\t\"stp x6, x7, [%[dst], #48]\\n\"\n+\t\t\t:\n+\t\t\t: [wdata] \"r\" (wdata), [dst] \"r\" (buf), [loc] \"r\" (addr)\n+\t\t\t: \"memory\", \"x0\", \"x1\", \"x2\", \"x3\", \"x4\", \"x5\", \"x6\",\n+\t\t\t \"x7\", \"x16\", \"x17\"\n+\t\t);\n+\t\tbreak;\n+\tcase 4:\n+\t\tasm volatile(\n+\t\t\t\".cpu generic+lse\\n\"\n+\t\t\t\"mov x16, %[wdata]\\n\"\n+\t\t\t\"mov x17, %[wdata]\\n\"\n+\t\t\t\"casp x0, x1, x16, x17, [%[loc]]\\n\"\n+\t\t\t\"casp x2, x3, x16, x17, [%[loc]]\\n\"\n+\t\t\t\"stp x0, x1, [%[dst]]\\n\"\n+\t\t\t\"stp x2, x3, [%[dst], #16]\\n\"\n+\t\t\t:\n+\t\t\t: [wdata] \"r\" (wdata), [dst] \"r\" (buf), [loc] \"r\" (addr)\n+\t\t\t: \"memory\", \"x0\", \"x1\", \"x2\", \"x3\", \"x16\", \"x17\"\n+\t\t);\n+\t\tbreak;\n+\tcase 2:\n+\t\tasm volatile(\n+\t\t\t\".cpu generic+lse\\n\"\n+\t\t\t\"mov x16, %[wdata]\\n\"\n+\t\t\t\"mov x17, %[wdata]\\n\"\n+\t\t\t\"casp x0, x1, x16, x17, [%[loc]]\\n\"\n+\t\t\t\"stp x0, x1, [%[dst]]\\n\"\n+\t\t\t:\n+\t\t\t: [wdata] \"r\" (wdata), [dst] \"r\" (buf), [loc] \"r\" (addr)\n+\t\t\t: \"memory\", \"x0\", \"x1\", \"x16\", \"x17\"\n+\t\t);\n+\t\tbreak;\n+\tcase 1:\n+\t\tbuf[0] = roc_npa_aura_op_alloc(aura_handle, drop);\n+\t\treturn !!buf[0];\n+\t}\n+\n+\t/* Pack the pointers */\n+\tfor (i = 0, count = 0; i < num; i++)\n+\t\tif (buf[i])\n+\t\t\tbuf[count++] = buf[i];\n+\n+\treturn count;\n+#else\n+\tunsigned int i, count;\n+\n+\tfor (i = 0, count = 0; i < num; i++) {\n+\t\tbuf[count] = roc_npa_aura_op_alloc(aura_handle, drop);\n+\t\tif (buf[count])\n+\t\t\tcount++;\n+\t}\n+\n+\treturn count;\n+#endif\n+}\n+\n+static inline unsigned int\n+roc_npa_aura_op_bulk_alloc(uint64_t aura_handle, uint64_t *buf,\n+\t\t\t unsigned int num, const int drop, const int partial)\n+{\n+\tunsigned int chunk, count, num_alloc;\n+\n+\tcount = 0;\n+\twhile (num) {\n+\t\tchunk = (num >= ROC_CN9K_NPA_BULK_ALLOC_MAX_PTRS) ?\n+\t\t\t\t ROC_CN9K_NPA_BULK_ALLOC_MAX_PTRS :\n+\t\t\t\t plt_align32prevpow2(num);\n+\n+\t\tnum_alloc =\n+\t\t\troc_npa_aura_bulk_alloc(aura_handle, buf, chunk, drop);\n+\n+\t\tcount += num_alloc;\n+\t\tbuf += num_alloc;\n+\t\tnum -= num_alloc;\n+\n+\t\tif (unlikely(num_alloc != chunk))\n+\t\t\tbreak;\n+\t}\n+\n+\t/* If the requested number of pointers was not allocated and if partial\n+\t * alloc is not desired, then free allocated pointers.\n+\t */\n+\tif (unlikely(num != 0 && !partial)) {\n+\t\troc_npa_aura_op_bulk_free(aura_handle, buf - count, count, 1);\n+\t\tcount = 0;\n+\t}\n+\n+\treturn count;\n+}\n+\n struct roc_npa {\n \tstruct plt_pci_device *pci_dev;\n \n", "prefixes": [ "13/52" ] }