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Update a patch.

GET /api/patches/88356/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 88356,
    "url": "http://patches.dpdk.org/api/patches/88356/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20210302072357.1657556-9-qi.z.zhang@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20210302072357.1657556-9-qi.z.zhang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20210302072357.1657556-9-qi.z.zhang@intel.com",
    "date": "2021-03-02T07:23:51",
    "name": "[08/14] net/ice/base: support GTPU IP inner IPv6 for FDIR",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "40dacc50725724d7c5d4cfe7095ed1b4f41ce953",
    "submitter": {
        "id": 504,
        "url": "http://patches.dpdk.org/api/people/504/?format=api",
        "name": "Qi Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "delegate": {
        "id": 1540,
        "url": "http://patches.dpdk.org/api/users/1540/?format=api",
        "username": "qzhan15",
        "first_name": "Qi",
        "last_name": "Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20210302072357.1657556-9-qi.z.zhang@intel.com/mbox/",
    "series": [
        {
            "id": 15435,
            "url": "http://patches.dpdk.org/api/series/15435/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=15435",
            "date": "2021-03-02T07:23:43",
            "name": "ice: base code update",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/15435/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/88356/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/88356/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 59A17A054F;\n\tTue,  2 Mar 2021 08:21:09 +0100 (CET)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 4D5521CC575;\n\tTue,  2 Mar 2021 08:20:37 +0100 (CET)",
            "from mga03.intel.com (mga03.intel.com [134.134.136.65])\n by mails.dpdk.org (Postfix) with ESMTP id 690461CC574\n for <dev@dpdk.org>; Tue,  2 Mar 2021 08:20:34 +0100 (CET)",
            "from fmsmga001.fm.intel.com ([10.253.24.23])\n by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 01 Mar 2021 23:20:33 -0800",
            "from dpdk51.sh.intel.com ([10.67.111.142])\n by fmsmga001.fm.intel.com with ESMTP; 01 Mar 2021 23:20:30 -0800"
        ],
        "IronPort-SDR": [
            "\n N2TDn/l05wM3ead3CiYYxdKlnXrB9Qi0vujA0+oduqkJHupLGyqGpPQ1TzOuVEAIyxSYz9gKBu\n 2z6ZlYgVUzeg==",
            "\n k0IEPRKD7NVYMS/ltrcccN0aetuVOnvrx5YGJ+3ha1fvkuZQw8T/TrTd7y5sIDfFV1QJ2KPdmB\n mjK17TD3icDg=="
        ],
        "X-IronPort-AV": [
            "E=McAfee;i=\"6000,8403,9910\"; a=\"186775296\"",
            "E=Sophos;i=\"5.81,216,1610438400\"; d=\"scan'208\";a=\"186775296\"",
            "E=Sophos;i=\"5.81,216,1610438400\"; d=\"scan'208\";a=\"506230357\""
        ],
        "X-ExtLoop1": "1",
        "From": "Qi Zhang <qi.z.zhang@intel.com>",
        "To": "qiming.yang@intel.com",
        "Cc": "dev@dpdk.org, haiyue.wang@intel.com, junfeng.guo@intel.com,\n Qi Zhang <qi.z.zhang@intel.com>",
        "Date": "Tue,  2 Mar 2021 15:23:51 +0800",
        "Message-Id": "<20210302072357.1657556-9-qi.z.zhang@intel.com>",
        "X-Mailer": "git-send-email 2.26.2",
        "In-Reply-To": "<20210302072357.1657556-1-qi.z.zhang@intel.com>",
        "References": "<20210302072357.1657556-1-qi.z.zhang@intel.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Subject": "[dpdk-dev] [PATCH 08/14] net/ice/base: support GTPU IP inner IPv6\n for FDIR",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Support IPV4_GTPU with inner IPV6/UDP/TCP for FDIR.\n\nSigned-off-by: Junfeng Guo <junfeng.guo@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_fdir.c | 106 ++++++++++++++++++++++++++++++++\n drivers/net/ice/base/ice_fdir.h |   9 +++\n drivers/net/ice/base/ice_type.h |   3 +\n 3 files changed, 118 insertions(+)",
    "diff": "diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c\nindex 3df3de1bdb..689e96da1e 100644\n--- a/drivers/net/ice/base/ice_fdir.c\n+++ b/drivers/net/ice/base/ice_fdir.c\n@@ -249,6 +249,54 @@ static const u8 ice_fdir_icmp4_gtpu4_pkt[] = {\n \t0x00, 0x00,\n };\n \n+static const u8 ice_fdir_ipv6_gtpu4_pkt[] = {\n+\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,\n+\t0x00, 0x4c, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,\n+\t0x7c, 0x9e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x38,\n+\t0x24, 0x42, 0x30, 0xff, 0x00, 0x28, 0x00, 0x00,\n+\t0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t0x3b, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00,\n+};\n+\n+static const u8 ice_fdir_udp6_gtpu4_pkt[] = {\n+\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,\n+\t0x00, 0x54, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,\n+\t0x7c, 0x96, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x40,\n+\t0x4e, 0x3d, 0x30, 0xff, 0x00, 0x30, 0x00, 0x00,\n+\t0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08,\n+\t0x11, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,\n+\t0xff, 0xdc, 0x00, 0x00,\n+};\n+\n+static const u8 ice_fdir_tcp6_gtpu4_pkt[] = {\n+\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,\n+\t0x00, 0x62, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,\n+\t0x7c, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x08, 0x68, 0x08, 0x68, 0x00, 0x4e,\n+\t0x59, 0x08, 0x30, 0xff, 0x00, 0x3e, 0x00, 0x00,\n+\t0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x16,\n+\t0x06, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x14, 0x00, 0x50, 0x00, 0x00,\n+\t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x02,\n+\t0x20, 0x00, 0x8f, 0x7b, 0x00, 0x00, 0x00, 0x00,\n+};\n+\n static const u8 ice_fdir_ipv6_gtpu6_pkt[] = {\n \t0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n \t0x00, 0x00, 0x00, 0x00, 0x86, 0xdd, 0x60, 0x00,\n@@ -802,6 +850,27 @@ static const struct ice_fdir_base_pkt ice_fdir_pkt[] = {\n \t\tsizeof(ice_fdir_ipv4_gtpu4_pkt),\n \t\tice_fdir_ipv4_gtpu4_pkt,\n \t},\n+\t{\n+\t\tICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6,\n+\t\tsizeof(ice_fdir_ipv6_gtpu4_pkt),\n+\t\tice_fdir_ipv6_gtpu4_pkt,\n+\t\tsizeof(ice_fdir_ipv6_gtpu4_pkt),\n+\t\tice_fdir_ipv6_gtpu4_pkt,\n+\t},\n+\t{\n+\t\tICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_UDP,\n+\t\tsizeof(ice_fdir_udp6_gtpu4_pkt),\n+\t\tice_fdir_udp6_gtpu4_pkt,\n+\t\tsizeof(ice_fdir_udp6_gtpu4_pkt),\n+\t\tice_fdir_udp6_gtpu4_pkt,\n+\t},\n+\t{\n+\t\tICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_TCP,\n+\t\tsizeof(ice_fdir_tcp6_gtpu4_pkt),\n+\t\tice_fdir_tcp6_gtpu4_pkt,\n+\t\tsizeof(ice_fdir_tcp6_gtpu4_pkt),\n+\t\tice_fdir_tcp6_gtpu4_pkt,\n+\t},\n \t{\n \t\tICE_FLTR_PTYPE_NONF_IPV6_GTPU,\n \t\tsizeof(ice_fdir_ipv6_gtpu6_pkt),\n@@ -1391,6 +1460,9 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input,\n \t\tcase ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4:\n \t\tcase ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP:\n \t\tcase ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP:\n+\t\tcase ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6:\n+\t\tcase ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_UDP:\n+\t\tcase ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_TCP:\n \t\t\tice_memcpy(pkt, ice_fdir_pkt[idx].tun_pkt,\n \t\t\t\t   ice_fdir_pkt[idx].tun_pkt_len,\n \t\t\t\t   ICE_NONDMA_TO_NONDMA);\n@@ -1575,6 +1647,40 @@ ice_fdir_get_gen_prgm_pkt(struct ice_hw *hw, struct ice_fdir_fltr *input,\n \t\tice_pkt_insert_u8(loc, ICE_IPV4_NO_MAC_TOS_OFFSET, input->ip.v4.tos);\n \t\tice_pkt_insert_u8(loc, ICE_IPV4_NO_MAC_TTL_OFFSET, input->ip.v4.ttl);\n \t\tbreak;\n+\tcase ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6:\n+\t\tice_pkt_insert_ipv6_addr(loc, ICE_IPV6_NO_MAC_DST_ADDR_OFFSET,\n+\t\t\t\t\t input->ip.v6.src_ip);\n+\t\tice_pkt_insert_ipv6_addr(loc, ICE_IPV6_NO_MAC_SRC_ADDR_OFFSET,\n+\t\t\t\t\t input->ip.v6.dst_ip);\n+\t\tice_pkt_insert_u8_tc(loc, ICE_IPV6_NO_MAC_TC_OFFSET, input->ip.v6.tc);\n+\t\tice_pkt_insert_u8(loc, ICE_IPV6_NO_MAC_HLIM_OFFSET, input->ip.v6.hlim);\n+\t\tice_pkt_insert_u8(loc, ICE_IPV6_NO_MAC_PROTO_OFFSET,\n+\t\t\t\t  input->ip.v6.proto);\n+\t\tbreak;\n+\tcase ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_UDP:\n+\t\tice_pkt_insert_ipv6_addr(loc, ICE_IPV6_NO_MAC_DST_ADDR_OFFSET,\n+\t\t\t\t\t input->ip.v6.src_ip);\n+\t\tice_pkt_insert_ipv6_addr(loc, ICE_IPV6_NO_MAC_SRC_ADDR_OFFSET,\n+\t\t\t\t\t input->ip.v6.dst_ip);\n+\t\tice_pkt_insert_u16(loc, ICE_UDP6_NO_MAC_DST_PORT_OFFSET,\n+\t\t\t\t   input->ip.v6.src_port);\n+\t\tice_pkt_insert_u16(loc, ICE_UDP6_NO_MAC_SRC_PORT_OFFSET,\n+\t\t\t\t   input->ip.v6.dst_port);\n+\t\tice_pkt_insert_u8_tc(loc, ICE_IPV6_NO_MAC_TC_OFFSET, input->ip.v6.tc);\n+\t\tice_pkt_insert_u8(loc, ICE_IPV6_NO_MAC_HLIM_OFFSET, input->ip.v6.hlim);\n+\t\tbreak;\n+\tcase ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_TCP:\n+\t\tice_pkt_insert_ipv6_addr(loc, ICE_IPV6_NO_MAC_DST_ADDR_OFFSET,\n+\t\t\t\t\t input->ip.v6.src_ip);\n+\t\tice_pkt_insert_ipv6_addr(loc, ICE_IPV6_NO_MAC_SRC_ADDR_OFFSET,\n+\t\t\t\t\t input->ip.v6.dst_ip);\n+\t\tice_pkt_insert_u16(loc, ICE_TCP6_NO_MAC_DST_PORT_OFFSET,\n+\t\t\t\t   input->ip.v6.src_port);\n+\t\tice_pkt_insert_u16(loc, ICE_TCP6_NO_MAC_SRC_PORT_OFFSET,\n+\t\t\t\t   input->ip.v6.dst_port);\n+\t\tice_pkt_insert_u8_tc(loc, ICE_IPV6_NO_MAC_TC_OFFSET, input->ip.v6.tc);\n+\t\tice_pkt_insert_u8(loc, ICE_IPV6_NO_MAC_HLIM_OFFSET, input->ip.v6.hlim);\n+\t\tbreak;\n \tcase ICE_FLTR_PTYPE_NONF_IPV6_GTPU:\n \tcase ICE_FLTR_PTYPE_NONF_IPV6_GTPU_IPV6_OTHER:\n \t\tice_pkt_insert_ipv6_addr(loc, ICE_IPV6_DST_ADDR_OFFSET,\ndiff --git a/drivers/net/ice/base/ice_fdir.h b/drivers/net/ice/base/ice_fdir.h\nindex e236f13f05..6573f96bc1 100644\n--- a/drivers/net/ice/base/ice_fdir.h\n+++ b/drivers/net/ice/base/ice_fdir.h\n@@ -56,6 +56,15 @@\n #define ICE_TCP4_NO_MAC_DST_PORT_OFFSET\t22\n #define ICE_UDP4_NO_MAC_SRC_PORT_OFFSET\t20\n #define ICE_UDP4_NO_MAC_DST_PORT_OFFSET\t22\n+#define ICE_IPV6_NO_MAC_TC_OFFSET\t0\n+#define ICE_IPV6_NO_MAC_HLIM_OFFSET\t7\n+#define ICE_IPV6_NO_MAC_PROTO_OFFSET\t6\n+#define ICE_IPV6_NO_MAC_SRC_ADDR_OFFSET\t8\n+#define ICE_IPV6_NO_MAC_DST_ADDR_OFFSET\t24\n+#define ICE_TCP6_NO_MAC_SRC_PORT_OFFSET\t40\n+#define ICE_TCP6_NO_MAC_DST_PORT_OFFSET\t42\n+#define ICE_UDP6_NO_MAC_SRC_PORT_OFFSET\t40\n+#define ICE_UDP6_NO_MAC_DST_PORT_OFFSET\t42\n #define ICE_IPV4_GTPU_TEID_OFFSET\t46\n #define ICE_IPV4_GTPU_QFI_OFFSET\t56\n #define ICE_IPV6_GTPU_TEID_OFFSET\t66\ndiff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h\nindex 102c209286..2550e0e19f 100644\n--- a/drivers/net/ice/base/ice_type.h\n+++ b/drivers/net/ice/base/ice_type.h\n@@ -316,6 +316,9 @@ enum ice_fltr_ptype {\n \tICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4,\n \tICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP,\n \tICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP,\n+\tICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6,\n+\tICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_UDP,\n+\tICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_TCP,\n \tICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4,\n \tICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_UDP,\n \tICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_TCP,\n",
    "prefixes": [
        "08/14"
    ]
}