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GET /api/patches/86283/?format=api
{ "id": 86283, "url": "http://patches.dpdk.org/api/patches/86283/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1610373560-253158-2-git-send-email-matan@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1610373560-253158-2-git-send-email-matan@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1610373560-253158-2-git-send-email-matan@nvidia.com", "date": "2021-01-11T13:59:11", "name": "[01/10] common/mlx5: add DevX attributes for compress", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "f7a03059dfc3f376ff0c8c30624a004c7622fe10", "submitter": { "id": 1911, "url": "http://patches.dpdk.org/api/people/1911/?format=api", "name": "Matan Azrad", "email": "matan@nvidia.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1610373560-253158-2-git-send-email-matan@nvidia.com/mbox/", "series": [ { "id": 14634, "url": "http://patches.dpdk.org/api/series/14634/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=14634", "date": "2021-01-11T13:59:10", "name": "add mlx5 compress PMD", "version": 1, "mbox": "http://patches.dpdk.org/series/14634/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/86283/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/86283/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 401BCA09FF;\n\tMon, 11 Jan 2021 14:59:34 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2A2D2140CEE;\n\tMon, 11 Jan 2021 14:59:34 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by mails.dpdk.org (Postfix) with ESMTP id 1CE8C140CD7\n for <dev@dpdk.org>; Mon, 11 Jan 2021 14:59:32 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n matan@nvidia.com) with SMTP; 11 Jan 2021 15:59:29 +0200", "from pegasus25.mtr.labs.mlnx. (pegasus25.mtr.labs.mlnx\n [10.210.16.10])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 10BDxPKI010436;\n Mon, 11 Jan 2021 15:59:29 +0200" ], "From": "Matan Azrad <matan@nvidia.com>", "To": "dev@dpdk.org", "Cc": "Thomas Monjalon <thomas@monjalon.net>,\n Ashish Gupta <ashish.gupta@marvell.com>,\n Fiona Trahe <fiona.trahe@intel.com>", "Date": "Mon, 11 Jan 2021 13:59:11 +0000", "Message-Id": "<1610373560-253158-2-git-send-email-matan@nvidia.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1610373560-253158-1-git-send-email-matan@nvidia.com>", "References": "<1610373560-253158-1-git-send-email-matan@nvidia.com>", "Subject": "[dpdk-dev] [PATCH 01/10] common/mlx5: add DevX attributes for\n compress", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add the DevX attributes for compress related engiens:\n\tcompress\n\tdecompress\n\tdma\n\nSigned-off-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 10 ++++++++++\n drivers/common/mlx5/mlx5_devx_cmds.h | 7 +++++++\n drivers/common/mlx5/mlx5_prm.h | 18 ++++++++++++++++--\n 3 files changed, 33 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 790a701..84a835d 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -725,6 +725,16 @@ struct mlx5_devx_obj *\n \tattr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd);\n \tattr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq);\n \tattr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz);\n+\tattr->mmo_dma_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo);\n+\tattr->mmo_compress_en = MLX5_GET(cmd_hca_cap, hcattr, compress);\n+\tattr->mmo_decompress_en = MLX5_GET(cmd_hca_cap, hcattr, decompress);\n+\tattr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr,\n+\t\t\t\t\t\t compress_min_block_size);\n+\tattr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size);\n+\tattr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr,\n+\t\t\t\t\t log_compress_mmo_size);\n+\tattr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr,\n+\t\t\t\t\t\tlog_decompress_mmo_size);\n \tif (attr->qos.sup) {\n \t\tMLX5_SET(query_hca_cap_in, in, op_mod,\n \t\t\t MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex a14f3bf..a279422 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -127,6 +127,13 @@ struct mlx5_hca_attr {\n \tuint32_t log_max_srq;\n \tuint32_t log_max_srq_sz;\n \tuint32_t rss_ind_tbl_cap;\n+\tuint32_t mmo_dma_en:1;\n+\tuint32_t mmo_compress_en:1;\n+\tuint32_t mmo_decompress_en:1;\n+\tuint32_t compress_min_block_size:4;\n+\tuint32_t log_max_mmo_dma:5;\n+\tuint32_t log_max_mmo_compress:5;\n+\tuint32_t log_max_mmo_decompress:5;\n };\n \n struct mlx5_devx_wq_attr {\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 8c9b53c..6f5a6cf 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -1120,7 +1120,15 @@ enum {\n struct mlx5_ifc_cmd_hca_cap_bits {\n \tu8 reserved_at_0[0x30];\n \tu8 vhca_id[0x10];\n-\tu8 reserved_at_40[0x40];\n+\tu8 reserved_at_40[0x20];\n+\tu8 reserved_at_60[0x3];\n+\tu8 log_regexp_scatter_gather_size[0x5];\n+\tu8 reserved_at_68[0x3];\n+\tu8 log_dma_mmo_size[5];\n+\tu8 reserved_at_70[0x3];\n+\tu8 log_compress_mmo_size[5];\n+\tu8 reserved_at_78[0x3];\n+\tu8 log_decompress_mmo_size[5];\n \tu8 log_max_srq_sz[0x8];\n \tu8 log_max_qp_sz[0x8];\n \tu8 reserved_at_90[0x9];\n@@ -1168,7 +1176,13 @@ struct mlx5_ifc_cmd_hca_cap_bits {\n \tu8 log_max_ra_res_dc[0x6];\n \tu8 reserved_at_140[0xa];\n \tu8 log_max_ra_req_qp[0x6];\n-\tu8 reserved_at_150[0xa];\n+\tu8 rtr2rts_qp_counters_set_id[1];\n+\tu8 rts2rts_udp_sport[1];\n+\tu8 rts2rts_lag_tx_port_affinity[1];\n+\tu8 dma_mmo[1];\n+\tu8 compress_min_block_size[4];\n+\tu8 compress[1];\n+\tu8 decompress[1];\n \tu8 log_max_ra_res_qp[0x6];\n \tu8 end_pad[0x1];\n \tu8 cc_query_allowed[0x1];\n", "prefixes": [ "01/10" ] }