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GET /api/patches/86036/?format=api
{ "id": 86036, "url": "http://patches.dpdk.org/api/patches/86036/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1609921181-5019-12-git-send-email-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1609921181-5019-12-git-send-email-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1609921181-5019-12-git-send-email-michaelba@nvidia.com", "date": "2021-01-06T08:19:33", "name": "[v3,11/19] common/mlx5: enhance page size configuration", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "b98379a5a8afab0a3c6ac175181ed65ee449133c", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1609921181-5019-12-git-send-email-michaelba@nvidia.com/mbox/", "series": [ { "id": 14550, "url": "http://patches.dpdk.org/api/series/14550/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=14550", "date": "2021-01-06T08:19:22", "name": "common/mlx5: share DevX resources creations", "version": 3, "mbox": "http://patches.dpdk.org/series/14550/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/86036/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/86036/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (xvm-189-124.dc0.ghst.net [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2A94BA09FF;\n\tWed, 6 Jan 2021 09:22:02 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7D5E41606D8;\n\tWed, 6 Jan 2021 09:21:24 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by mails.dpdk.org (Postfix) with ESMTP id 154DF1608C4\n for <dev@dpdk.org>; Wed, 6 Jan 2021 09:21:22 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n michaelba@nvidia.com) with SMTP; 6 Jan 2021 10:21:17 +0200", "from nvidia.com (pegasus07.mtr.labs.mlnx [10.210.16.112])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 1068KAge009291;\n Wed, 6 Jan 2021 10:21:17 +0200" ], "From": "Michael Baum <michaelba@nvidia.com>", "To": "dev@dpdk.org", "Cc": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "Date": "Wed, 6 Jan 2021 08:19:33 +0000", "Message-Id": "<1609921181-5019-12-git-send-email-michaelba@nvidia.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1609921181-5019-1-git-send-email-michaelba@nvidia.com>", "References": "<1609231944-29274-2-git-send-email-michaelba@nvidia.com>\n <1609921181-5019-1-git-send-email-michaelba@nvidia.com>", "Subject": "[dpdk-dev] [PATCH v3 11/19] common/mlx5: enhance page size\n configuration", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The PRM calculates page size in 4K, so need to reduce the log_wq_pg_sz\nattribute.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 53 ++++++++++++++++--------------------\n 1 file changed, 23 insertions(+), 30 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 59f0bcc..790a701 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -268,9 +268,8 @@ struct mlx5_devx_obj *\n \tMLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);\n \tMLX5_SET(mkc, mkc, translations_octword_size, translation_size);\n \tMLX5_SET(mkc, mkc, relaxed_ordering_write,\n-\t\tattr->relaxed_ordering_write);\n-\tMLX5_SET(mkc, mkc, relaxed_ordering_read,\n-\t\tattr->relaxed_ordering_read);\n+\t\t attr->relaxed_ordering_write);\n+\tMLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read);\n \tMLX5_SET64(mkc, mkc, start_addr, attr->addr);\n \tMLX5_SET64(mkc, mkc, len, attr->size);\n \tmkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out,\n@@ -308,7 +307,7 @@ struct mlx5_devx_obj *\n \tif (status) {\n \t\tint syndrome = MLX5_GET(query_flow_counter_out, out, syndrome);\n \n-\t\tDRV_LOG(ERR, \"Bad devX status %x, syndrome = %x\", status,\n+\t\tDRV_LOG(ERR, \"Bad DevX status %x, syndrome = %x\", status,\n \t\t\tsyndrome);\n \t}\n \treturn status;\n@@ -374,8 +373,7 @@ struct mlx5_devx_obj *\n \tsyndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome);\n \tif (status) {\n \t\tDRV_LOG(DEBUG, \"Failed to query NIC vport context, \"\n-\t\t\t\"status %x, syndrome = %x\",\n-\t\t\tstatus, syndrome);\n+\t\t\t\"status %x, syndrome = %x\", status, syndrome);\n \t\treturn -1;\n \t}\n \tvctx = MLX5_ADDR_OF(query_nic_vport_context_out, out,\n@@ -662,8 +660,7 @@ struct mlx5_devx_obj *\n \tsyndrome = MLX5_GET(query_hca_cap_out, out, syndrome);\n \tif (status) {\n \t\tDRV_LOG(DEBUG, \"Failed to query devx HCA capabilities, \"\n-\t\t\t\"status %x, syndrome = %x\",\n-\t\t\tstatus, syndrome);\n+\t\t\t\"status %x, syndrome = %x\", status, syndrome);\n \t\treturn -1;\n \t}\n \thcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);\n@@ -683,11 +680,11 @@ struct mlx5_devx_obj *\n \t\t(cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz);\n \tattr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id);\n \tattr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr,\n-\t\t\trelaxed_ordering_write);\n+\t\t\t\t\t\trelaxed_ordering_write);\n \tattr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr,\n-\t\t\trelaxed_ordering_read);\n+\t\t\t\t\t relaxed_ordering_read);\n \tattr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr,\n-\t\t\taccess_register_user);\n+\t\t\t\t\t access_register_user);\n \tattr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,\n \t\t\t\t\t eth_net_offloads);\n \tattr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);\n@@ -738,8 +735,7 @@ struct mlx5_devx_obj *\n \t\t\tgoto error;\n \t\tif (status) {\n \t\t\tDRV_LOG(DEBUG, \"Failed to query devx QOS capabilities,\"\n-\t\t\t\t\" status %x, syndrome = %x\",\n-\t\t\t\tstatus, syndrome);\n+\t\t\t\t\" status %x, syndrome = %x\", status, syndrome);\n \t\t\treturn -1;\n \t\t}\n \t\thcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);\n@@ -769,17 +765,14 @@ struct mlx5_devx_obj *\n \t\t MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE |\n \t\t MLX5_HCA_CAP_OPMOD_GET_CUR);\n \n-\trc = mlx5_glue->devx_general_cmd(ctx,\n-\t\t\t\t\t in, sizeof(in),\n-\t\t\t\t\t out, sizeof(out));\n+\trc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));\n \tif (rc)\n \t\tgoto error;\n \tstatus = MLX5_GET(query_hca_cap_out, out, status);\n \tsyndrome = MLX5_GET(query_hca_cap_out, out, syndrome);\n \tif (status) {\n \t\tDRV_LOG(DEBUG, \"Failed to query devx HCA capabilities, \"\n-\t\t\t\"status %x, syndrome = %x\",\n-\t\t\tstatus, syndrome);\n+\t\t\t\"status %x, syndrome = %x\", status, syndrome);\n \t\tattr->log_max_ft_sampler_num = 0;\n \t\treturn -1;\n \t}\n@@ -796,9 +789,7 @@ struct mlx5_devx_obj *\n \t\t MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS |\n \t\t MLX5_HCA_CAP_OPMOD_GET_CUR);\n \n-\trc = mlx5_glue->devx_general_cmd(ctx,\n-\t\t\t\t\t in, sizeof(in),\n-\t\t\t\t\t out, sizeof(out));\n+\trc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));\n \tif (rc) {\n \t\tattr->eth_net_offloads = 0;\n \t\tgoto error;\n@@ -807,8 +798,7 @@ struct mlx5_devx_obj *\n \tsyndrome = MLX5_GET(query_hca_cap_out, out, syndrome);\n \tif (status) {\n \t\tDRV_LOG(DEBUG, \"Failed to query devx HCA capabilities, \"\n-\t\t\t\"status %x, syndrome = %x\",\n-\t\t\tstatus, syndrome);\n+\t\t\t\"status %x, syndrome = %x\", status, syndrome);\n \t\tattr->eth_net_offloads = 0;\n \t\treturn -1;\n \t}\n@@ -927,7 +917,9 @@ struct mlx5_devx_obj *\n \tMLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter);\n \tMLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter);\n \tMLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride);\n-\tMLX5_SET(wq, wq_ctx, log_wq_pg_sz, wq_attr->log_wq_pg_sz);\n+\tif (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT)\n+\t\tMLX5_SET(wq, wq_ctx, log_wq_pg_sz,\n+\t\t\t wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT);\n \tMLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz);\n \tMLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid);\n \tMLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid);\n@@ -1574,13 +1566,13 @@ struct mlx5_devx_obj *\n \tMLX5_SET(cqc, cqctx, cc, attr->use_first_only);\n \tMLX5_SET(cqc, cqctx, oi, attr->overrun_ignore);\n \tMLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size);\n-\tMLX5_SET(cqc, cqctx, log_page_size, attr->log_page_size -\n-\t\t MLX5_ADAPTER_PAGE_SHIFT);\n+\tif (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)\n+\t\tMLX5_SET(cqc, cqctx, log_page_size,\n+\t\t\t attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);\n \tMLX5_SET(cqc, cqctx, c_eqn, attr->eqn);\n \tMLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id);\n \tMLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en);\n-\tMLX5_SET(cqc, cqctx, mini_cqe_res_format,\n-\t\t attr->mini_cqe_res_format);\n+\tMLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format);\n \tMLX5_SET(cqc, cqctx, mini_cqe_res_format_ext,\n \t\t attr->mini_cqe_res_format_ext);\n \tif (attr->q_umem_valid) {\n@@ -1809,8 +1801,9 @@ struct mlx5_devx_obj *\n \tif (attr->uar_index) {\n \t\tMLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);\n \t\tMLX5_SET(qpc, qpc, uar_page, attr->uar_index);\n-\t\tMLX5_SET(qpc, qpc, log_page_size, attr->log_page_size -\n-\t\t\t MLX5_ADAPTER_PAGE_SHIFT);\n+\t\tif (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)\n+\t\t\tMLX5_SET(qpc, qpc, log_page_size,\n+\t\t\t\t attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);\n \t\tif (attr->sq_size) {\n \t\t\tMLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size));\n \t\t\tMLX5_SET(qpc, qpc, cqn_snd, attr->cqn);\n", "prefixes": [ "v3", "11/19" ] }