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GET /api/patches/86033/?format=api
{ "id": 86033, "url": "http://patches.dpdk.org/api/patches/86033/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1609921181-5019-10-git-send-email-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1609921181-5019-10-git-send-email-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1609921181-5019-10-git-send-email-michaelba@nvidia.com", "date": "2021-01-06T08:19:31", "name": "[v3,09/19] net/mlx5: move Tx CQ creation to common", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "af187141340e269e911bf6b07e6bb7e91a5f0f8c", "submitter": { "id": 1949, "url": "http://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1609921181-5019-10-git-send-email-michaelba@nvidia.com/mbox/", "series": [ { "id": 14550, "url": "http://patches.dpdk.org/api/series/14550/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=14550", "date": "2021-01-06T08:19:22", "name": "common/mlx5: share DevX resources creations", "version": 3, "mbox": "http://patches.dpdk.org/series/14550/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/86033/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/86033/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (xvm-189-124.dc0.ghst.net [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id EA710A09FF;\n\tWed, 6 Jan 2021 09:21:33 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 89ED81608E7;\n\tWed, 6 Jan 2021 09:21:15 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by mails.dpdk.org (Postfix) with ESMTP id 5482B160830\n for <dev@dpdk.org>; Wed, 6 Jan 2021 09:21:12 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n michaelba@nvidia.com) with SMTP; 6 Jan 2021 10:21:09 +0200", "from nvidia.com (pegasus07.mtr.labs.mlnx [10.210.16.112])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 1068KAgc009291;\n Wed, 6 Jan 2021 10:21:09 +0200" ], "From": "Michael Baum <michaelba@nvidia.com>", "To": "dev@dpdk.org", "Cc": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "Date": "Wed, 6 Jan 2021 08:19:31 +0000", "Message-Id": "<1609921181-5019-10-git-send-email-michaelba@nvidia.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1609921181-5019-1-git-send-email-michaelba@nvidia.com>", "References": "<1609231944-29274-2-git-send-email-michaelba@nvidia.com>\n <1609921181-5019-1-git-send-email-michaelba@nvidia.com>", "Subject": "[dpdk-dev] [PATCH v3 09/19] net/mlx5: move Tx CQ creation to common", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Using common function for Tx CQ creation.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/mlx5.h | 6 +-\n drivers/net/mlx5/mlx5_devx.c | 178 +++++++------------------------------------\n 2 files changed, 29 insertions(+), 155 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex f889180..e61154b 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -847,11 +847,7 @@ struct mlx5_txq_obj {\n \t\t};\n \t\tstruct {\n \t\t\tstruct rte_eth_dev *dev;\n-\t\t\tstruct mlx5_devx_obj *cq_devx;\n-\t\t\tvoid *cq_umem;\n-\t\t\tvoid *cq_buf;\n-\t\t\tint64_t cq_dbrec_offset;\n-\t\t\tstruct mlx5_devx_dbr_page *cq_dbrec_page;\n+\t\t\tstruct mlx5_devx_cq cq_obj;\n \t\t\tstruct mlx5_devx_obj *sq_devx;\n \t\t\tvoid *sq_umem;\n \t\t\tvoid *sq_buf;\ndiff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c\nindex 5c5bea6..af0383c 100644\n--- a/drivers/net/mlx5/mlx5_devx.c\n+++ b/drivers/net/mlx5/mlx5_devx.c\n@@ -15,6 +15,7 @@\n \n #include <mlx5_glue.h>\n #include <mlx5_devx_cmds.h>\n+#include <mlx5_common_devx.h>\n #include <mlx5_malloc.h>\n \n #include \"mlx5.h\"\n@@ -1141,28 +1142,6 @@\n }\n \n /**\n- * Release DevX Tx CQ resources.\n- *\n- * @param txq_obj\n- * DevX Tx queue object.\n- */\n-static void\n-mlx5_txq_release_devx_cq_resources(struct mlx5_txq_obj *txq_obj)\n-{\n-\tif (txq_obj->cq_devx)\n-\t\tclaim_zero(mlx5_devx_cmd_destroy(txq_obj->cq_devx));\n-\tif (txq_obj->cq_umem)\n-\t\tclaim_zero(mlx5_os_umem_dereg(txq_obj->cq_umem));\n-\tif (txq_obj->cq_buf)\n-\t\tmlx5_free(txq_obj->cq_buf);\n-\tif (txq_obj->cq_dbrec_page)\n-\t\tclaim_zero(mlx5_release_dbr(&txq_obj->txq_ctrl->priv->dbrpgs,\n-\t\t\t\t\t mlx5_os_get_umem_id\n-\t\t\t\t\t\t (txq_obj->cq_dbrec_page->umem),\n-\t\t\t\t\t txq_obj->cq_dbrec_offset));\n-}\n-\n-/**\n * Destroy the Tx queue DevX object.\n *\n * @param txq_obj\n@@ -1172,124 +1151,8 @@\n mlx5_txq_release_devx_resources(struct mlx5_txq_obj *txq_obj)\n {\n \tmlx5_txq_release_devx_sq_resources(txq_obj);\n-\tmlx5_txq_release_devx_cq_resources(txq_obj);\n-}\n-\n-/**\n- * Create a DevX CQ object and its resources for an Tx queue.\n- *\n- * @param dev\n- * Pointer to Ethernet device.\n- * @param idx\n- * Queue index in DPDK Tx queue array.\n- *\n- * @return\n- * Number of CQEs in CQ, 0 otherwise and rte_errno is set.\n- */\n-static uint32_t\n-mlx5_txq_create_devx_cq_resources(struct rte_eth_dev *dev, uint16_t idx)\n-{\n-\tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_txq_data *txq_data = (*priv->txqs)[idx];\n-\tstruct mlx5_txq_ctrl *txq_ctrl =\n-\t\t\tcontainer_of(txq_data, struct mlx5_txq_ctrl, txq);\n-\tstruct mlx5_txq_obj *txq_obj = txq_ctrl->obj;\n-\tstruct mlx5_devx_cq_attr cq_attr = { 0 };\n-\tstruct mlx5_cqe *cqe;\n-\tsize_t page_size;\n-\tsize_t alignment;\n-\tuint32_t cqe_n;\n-\tuint32_t i;\n-\tint ret;\n-\n-\tMLX5_ASSERT(txq_data);\n-\tMLX5_ASSERT(txq_obj);\n-\tpage_size = rte_mem_page_size();\n-\tif (page_size == (size_t)-1) {\n-\t\tDRV_LOG(ERR, \"Failed to get mem page size.\");\n-\t\trte_errno = ENOMEM;\n-\t\treturn 0;\n-\t}\n-\t/* Allocate memory buffer for CQEs. */\n-\talignment = MLX5_CQE_BUF_ALIGNMENT;\n-\tif (alignment == (size_t)-1) {\n-\t\tDRV_LOG(ERR, \"Failed to get CQE buf alignment.\");\n-\t\trte_errno = ENOMEM;\n-\t\treturn 0;\n-\t}\n-\t/* Create the Completion Queue. */\n-\tcqe_n = (1UL << txq_data->elts_n) / MLX5_TX_COMP_THRESH +\n-\t\t1 + MLX5_TX_COMP_THRESH_INLINE_DIV;\n-\tcqe_n = 1UL << log2above(cqe_n);\n-\tif (cqe_n > UINT16_MAX) {\n-\t\tDRV_LOG(ERR,\n-\t\t\t\"Port %u Tx queue %u requests to many CQEs %u.\",\n-\t\t\tdev->data->port_id, txq_data->idx, cqe_n);\n-\t\trte_errno = EINVAL;\n-\t\treturn 0;\n-\t}\n-\ttxq_obj->cq_buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO,\n-\t\t\t\t cqe_n * sizeof(struct mlx5_cqe),\n-\t\t\t\t alignment,\n-\t\t\t\t priv->sh->numa_node);\n-\tif (!txq_obj->cq_buf) {\n-\t\tDRV_LOG(ERR,\n-\t\t\t\"Port %u Tx queue %u cannot allocate memory (CQ).\",\n-\t\t\tdev->data->port_id, txq_data->idx);\n-\t\trte_errno = ENOMEM;\n-\t\treturn 0;\n-\t}\n-\t/* Register allocated buffer in user space with DevX. */\n-\ttxq_obj->cq_umem = mlx5_os_umem_reg(priv->sh->ctx,\n-\t\t\t\t\t\t(void *)txq_obj->cq_buf,\n-\t\t\t\t\t\tcqe_n * sizeof(struct mlx5_cqe),\n-\t\t\t\t\t\tIBV_ACCESS_LOCAL_WRITE);\n-\tif (!txq_obj->cq_umem) {\n-\t\trte_errno = errno;\n-\t\tDRV_LOG(ERR,\n-\t\t\t\"Port %u Tx queue %u cannot register memory (CQ).\",\n-\t\t\tdev->data->port_id, txq_data->idx);\n-\t\tgoto error;\n-\t}\n-\t/* Allocate doorbell record for completion queue. */\n-\ttxq_obj->cq_dbrec_offset = mlx5_get_dbr(priv->sh->ctx,\n-\t\t\t\t\t\t&priv->dbrpgs,\n-\t\t\t\t\t\t&txq_obj->cq_dbrec_page);\n-\tif (txq_obj->cq_dbrec_offset < 0) {\n-\t\trte_errno = errno;\n-\t\tDRV_LOG(ERR, \"Failed to allocate CQ door-bell.\");\n-\t\tgoto error;\n-\t}\n-\tcq_attr.uar_page_id = mlx5_os_get_devx_uar_page_id(priv->sh->tx_uar);\n-\tcq_attr.eqn = priv->sh->eqn;\n-\tcq_attr.q_umem_valid = 1;\n-\tcq_attr.q_umem_offset = (uintptr_t)txq_obj->cq_buf % page_size;\n-\tcq_attr.q_umem_id = mlx5_os_get_umem_id(txq_obj->cq_umem);\n-\tcq_attr.db_umem_valid = 1;\n-\tcq_attr.db_umem_offset = txq_obj->cq_dbrec_offset;\n-\tcq_attr.db_umem_id = mlx5_os_get_umem_id(txq_obj->cq_dbrec_page->umem);\n-\tcq_attr.log_cq_size = rte_log2_u32(cqe_n);\n-\tcq_attr.log_page_size = rte_log2_u32(page_size);\n-\t/* Create completion queue object with DevX. */\n-\ttxq_obj->cq_devx = mlx5_devx_cmd_create_cq(priv->sh->ctx, &cq_attr);\n-\tif (!txq_obj->cq_devx) {\n-\t\trte_errno = errno;\n-\t\tDRV_LOG(ERR, \"Port %u Tx queue %u CQ creation failure.\",\n-\t\t\tdev->data->port_id, idx);\n-\t\tgoto error;\n-\t}\n-\t/* Initial fill CQ buffer with invalid CQE opcode. */\n-\tcqe = (struct mlx5_cqe *)txq_obj->cq_buf;\n-\tfor (i = 0; i < cqe_n; i++) {\n-\t\tcqe->op_own = (MLX5_CQE_INVALID << 4) | MLX5_CQE_OWNER_MASK;\n-\t\t++cqe;\n-\t}\n-\treturn cqe_n;\n-error:\n-\tret = rte_errno;\n-\tmlx5_txq_release_devx_cq_resources(txq_obj);\n-\trte_errno = ret;\n-\treturn 0;\n+\tmlx5_devx_cq_destroy(&txq_obj->cq_obj);\n+\tmemset(&txq_obj->cq_obj, 0, sizeof(txq_obj->cq_obj));\n }\n \n /**\n@@ -1361,7 +1224,7 @@\n \tsq_attr.tis_lst_sz = 1;\n \tsq_attr.tis_num = priv->sh->tis->id;\n \tsq_attr.state = MLX5_SQC_STATE_RST;\n-\tsq_attr.cqn = txq_obj->cq_devx->id;\n+\tsq_attr.cqn = txq_obj->cq_obj.cq->id;\n \tsq_attr.flush_in_error_en = 1;\n \tsq_attr.allow_multi_pkt_send_wqe = !!priv->config.mps;\n \tsq_attr.allow_swp = !!priv->config.swp;\n@@ -1425,8 +1288,11 @@\n #else\n \tstruct mlx5_dev_ctx_shared *sh = priv->sh;\n \tstruct mlx5_txq_obj *txq_obj = txq_ctrl->obj;\n+\tstruct mlx5_devx_cq_attr cq_attr = {\n+\t\t.uar_page_id = mlx5_os_get_devx_uar_page_id(sh->tx_uar),\n+\t};\n \tvoid *reg_addr;\n-\tuint32_t cqe_n;\n+\tuint32_t cqe_n, log_desc_n;\n \tuint32_t wqe_n;\n \tint ret = 0;\n \n@@ -1434,19 +1300,31 @@\n \tMLX5_ASSERT(txq_obj);\n \ttxq_obj->txq_ctrl = txq_ctrl;\n \ttxq_obj->dev = dev;\n-\tcqe_n = mlx5_txq_create_devx_cq_resources(dev, idx);\n-\tif (!cqe_n) {\n-\t\trte_errno = errno;\n+\tcqe_n = (1UL << txq_data->elts_n) / MLX5_TX_COMP_THRESH +\n+\t\t1 + MLX5_TX_COMP_THRESH_INLINE_DIV;\n+\tlog_desc_n = log2above(cqe_n);\n+\tcqe_n = 1UL << log_desc_n;\n+\tif (cqe_n > UINT16_MAX) {\n+\t\tDRV_LOG(ERR, \"Port %u Tx queue %u requests to many CQEs %u.\",\n+\t\t\tdev->data->port_id, txq_data->idx, cqe_n);\n+\t\trte_errno = EINVAL;\n+\t\treturn 0;\n+\t}\n+\t/* Create completion queue object with DevX. */\n+\tret = mlx5_devx_cq_create(sh->ctx, &txq_obj->cq_obj, log_desc_n,\n+\t\t\t\t &cq_attr, priv->sh->numa_node);\n+\tif (ret) {\n+\t\tDRV_LOG(ERR, \"Port %u Tx queue %u CQ creation failure.\",\n+\t\t\tdev->data->port_id, idx);\n \t\tgoto error;\n \t}\n-\ttxq_data->cqe_n = log2above(cqe_n);\n-\ttxq_data->cqe_s = 1 << txq_data->cqe_n;\n+\ttxq_data->cqe_n = log_desc_n;\n+\ttxq_data->cqe_s = cqe_n;\n \ttxq_data->cqe_m = txq_data->cqe_s - 1;\n-\ttxq_data->cqes = (volatile struct mlx5_cqe *)txq_obj->cq_buf;\n+\ttxq_data->cqes = txq_obj->cq_obj.cqes;\n \ttxq_data->cq_ci = 0;\n \ttxq_data->cq_pi = 0;\n-\ttxq_data->cq_db = (volatile uint32_t *)(txq_obj->cq_dbrec_page->dbrs +\n-\t\t\t\t\t\ttxq_obj->cq_dbrec_offset);\n+\ttxq_data->cq_db = txq_obj->cq_obj.db_rec;\n \t*txq_data->cq_db = 0;\n \t/* Create Send Queue object with DevX. */\n \twqe_n = mlx5_txq_create_devx_sq_resources(dev, idx);\n", "prefixes": [ "v3", "09/19" ] }