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{
    "id": 86025,
    "url": "http://patches.dpdk.org/api/patches/86025/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1609921181-5019-2-git-send-email-michaelba@nvidia.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1609921181-5019-2-git-send-email-michaelba@nvidia.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1609921181-5019-2-git-send-email-michaelba@nvidia.com",
    "date": "2021-01-06T08:19:23",
    "name": "[v3,01/19] common/mlx5: fix completion queue entry size configuration",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "11010565e48e9842f4870271466bdc2d2e19417d",
    "submitter": {
        "id": 1949,
        "url": "http://patches.dpdk.org/api/people/1949/?format=api",
        "name": "Michael Baum",
        "email": "michaelba@nvidia.com"
    },
    "delegate": {
        "id": 3268,
        "url": "http://patches.dpdk.org/api/users/3268/?format=api",
        "username": "rasland",
        "first_name": "Raslan",
        "last_name": "Darawsheh",
        "email": "rasland@nvidia.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1609921181-5019-2-git-send-email-michaelba@nvidia.com/mbox/",
    "series": [
        {
            "id": 14550,
            "url": "http://patches.dpdk.org/api/series/14550/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=14550",
            "date": "2021-01-06T08:19:22",
            "name": "common/mlx5: share DevX resources creations",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/14550/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/86025/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/86025/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (xvm-189-124.dc0.ghst.net [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2835DA09FF;\n\tWed,  6 Jan 2021 09:20:28 +0100 (CET)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 11D42160863;\n\tWed,  6 Jan 2021 09:20:28 +0100 (CET)",
            "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by mails.dpdk.org (Postfix) with ESMTP id 671061607A2\n for <dev@dpdk.org>; Wed,  6 Jan 2021 09:20:26 +0100 (CET)",
            "from Internal Mail-Server by MTLPINE1 (envelope-from\n michaelba@nvidia.com) with SMTP; 6 Jan 2021 10:20:22 +0200",
            "from nvidia.com (pegasus07.mtr.labs.mlnx [10.210.16.112])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 1068KAgU009291;\n Wed, 6 Jan 2021 10:20:22 +0200"
        ],
        "From": "Michael Baum <michaelba@nvidia.com>",
        "To": "dev@dpdk.org",
        "Cc": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>, stable@dpdk.org",
        "Date": "Wed,  6 Jan 2021 08:19:23 +0000",
        "Message-Id": "<1609921181-5019-2-git-send-email-michaelba@nvidia.com>",
        "X-Mailer": "git-send-email 1.8.3.1",
        "In-Reply-To": "<1609921181-5019-1-git-send-email-michaelba@nvidia.com>",
        "References": "<1609231944-29274-2-git-send-email-michaelba@nvidia.com>\n <1609921181-5019-1-git-send-email-michaelba@nvidia.com>",
        "Subject": "[dpdk-dev] [PATCH v3 01/19] common/mlx5: fix completion queue entry\n size configuration",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "According to the current data-path implementation in the PMD the CQE\nsize must follow the cache-line size.\nSo, the configuration of the CQE size should be depended in\nRTE_CACHE_LINE_SIZE.\n\nWrongly, part of the CQE creations didn't follow it exactly what caused\nan incompatibility between HW and SW in the data-path when working in\n128B cache-line size systems.\n\nAdjust the rule for any CQE creation.\nRemove the cqe_size attribute from the DevX CQ creation command and set\nit inside the command translation according to the cache-line size.\n\nFixes: 79a7e409a2f6 (\"common/mlx5: prepare support of packet pacing\")\nFixes: 5cd0a83f413e (\"common/mlx5: support more fields in DevX CQ create\")\nCc: stable@dpdk.org\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 4 ++--\n drivers/common/mlx5/mlx5_devx_cmds.h | 1 -\n drivers/net/mlx5/mlx5_devx.c         | 4 ----\n drivers/net/mlx5/mlx5_txpp.c         | 4 ----\n 4 files changed, 2 insertions(+), 11 deletions(-)",
    "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 12f51a9..59f0bcc 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -1569,7 +1569,8 @@ struct mlx5_devx_obj *\n \t} else {\n \t\tMLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr);\n \t}\n-\tMLX5_SET(cqc, cqctx, cqe_sz, attr->cqe_size);\n+\tMLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ?\n+\t\t\t\t     MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B);\n \tMLX5_SET(cqc, cqctx, cc, attr->use_first_only);\n \tMLX5_SET(cqc, cqctx, oi, attr->overrun_ignore);\n \tMLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size);\n@@ -1582,7 +1583,6 @@ struct mlx5_devx_obj *\n \t\t attr->mini_cqe_res_format);\n \tMLX5_SET(cqc, cqctx, mini_cqe_res_format_ext,\n \t\t attr->mini_cqe_res_format_ext);\n-\tMLX5_SET(cqc, cqctx, cqe_sz, attr->cqe_size);\n \tif (attr->q_umem_valid) {\n \t\tMLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid);\n \t\tMLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id);\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex b335b7c..a14f3bf 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -277,7 +277,6 @@ struct mlx5_devx_cq_attr {\n \tuint32_t cqe_comp_en:1;\n \tuint32_t mini_cqe_res_format:2;\n \tuint32_t mini_cqe_res_format_ext:2;\n-\tuint32_t cqe_size:3;\n \tuint32_t log_cq_size:5;\n \tuint32_t log_page_size:5;\n \tuint32_t uar_page_id;\ndiff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c\nindex da3bb78..5c5bea6 100644\n--- a/drivers/net/mlx5/mlx5_devx.c\n+++ b/drivers/net/mlx5/mlx5_devx.c\n@@ -486,8 +486,6 @@\n \t\t\t\"Port %u Rx CQE compression is disabled for LRO.\",\n \t\t\tdev->data->port_id);\n \t}\n-\tif (priv->config.cqe_pad)\n-\t\tcq_attr.cqe_size = MLX5_CQE_SIZE_128B;\n \tlog_cqe_n = log2above(cqe_n);\n \tcq_size = sizeof(struct mlx5_cqe) * (1 << log_cqe_n);\n \tbuf = rte_calloc_socket(__func__, 1, cq_size, page_size,\n@@ -1262,8 +1260,6 @@\n \t\tDRV_LOG(ERR, \"Failed to allocate CQ door-bell.\");\n \t\tgoto error;\n \t}\n-\tcq_attr.cqe_size = (sizeof(struct mlx5_cqe) == 128) ?\n-\t\t\t    MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B;\n \tcq_attr.uar_page_id = mlx5_os_get_devx_uar_page_id(priv->sh->tx_uar);\n \tcq_attr.eqn = priv->sh->eqn;\n \tcq_attr.q_umem_valid = 1;\ndiff --git a/drivers/net/mlx5/mlx5_txpp.c b/drivers/net/mlx5/mlx5_txpp.c\nindex 726bdc6a..e998de3 100644\n--- a/drivers/net/mlx5/mlx5_txpp.c\n+++ b/drivers/net/mlx5/mlx5_txpp.c\n@@ -278,8 +278,6 @@\n \t\tgoto error;\n \t}\n \t/* Create completion queue object for Rearm Queue. */\n-\tcq_attr.cqe_size = (sizeof(struct mlx5_cqe) == 128) ?\n-\t\t\t    MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B;\n \tcq_attr.uar_page_id = mlx5_os_get_devx_uar_page_id(sh->tx_uar);\n \tcq_attr.eqn = sh->eqn;\n \tcq_attr.q_umem_valid = 1;\n@@ -516,8 +514,6 @@\n \t\tgoto error;\n \t}\n \t/* Create completion queue object for Clock Queue. */\n-\tcq_attr.cqe_size = (sizeof(struct mlx5_cqe) == 128) ?\n-\t\t\t    MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B;\n \tcq_attr.use_first_only = 1;\n \tcq_attr.overrun_ignore = 1;\n \tcq_attr.uar_page_id = mlx5_os_get_devx_uar_page_id(sh->tx_uar);\n",
    "prefixes": [
        "v3",
        "01/19"
    ]
}