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GET /api/patches/85916/?format=api
{ "id": 85916, "url": "http://patches.dpdk.org/api/patches/85916/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20201231072247.5719-6-pnalla@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201231072247.5719-6-pnalla@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201231072247.5719-6-pnalla@marvell.com", "date": "2020-12-31T07:22:37", "name": "[05/15] net/octeontx_ep: Add dev info get and configure", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ebe5f6767dfb294196061a79a5f03bb47a15c8f9", "submitter": { "id": 2074, "url": "http://patches.dpdk.org/api/people/2074/?format=api", "name": "Pradeep Nalla", "email": "pnalla@marvell.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20201231072247.5719-6-pnalla@marvell.com/mbox/", "series": [ { "id": 14507, "url": "http://patches.dpdk.org/api/series/14507/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=14507", "date": "2020-12-31T07:22:32", "name": "Octeon Tx/Tx2 Endpoint pmd", "version": 1, "mbox": "http://patches.dpdk.org/series/14507/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/85916/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/85916/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (xvm-189-124.dc0.ghst.net [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3853EA0A00;\n\tThu, 31 Dec 2020 08:23:26 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 34022140CF9;\n\tThu, 31 Dec 2020 08:23:03 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 7B01E140CE4\n for <dev@dpdk.org>; Thu, 31 Dec 2020 08:22:58 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 0BV7G5RC022206 for <dev@dpdk.org>; Wed, 30 Dec 2020 23:22:57 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com with ESMTP id 35rqgehx54-3\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Wed, 30 Dec 2020 23:22:57 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Wed, 30 Dec 2020 23:22:56 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Wed, 30 Dec 2020 23:22:56 -0800", "from localhost.localdomain (unknown [10.111.145.157])\n by maili.marvell.com (Postfix) with ESMTP id 227C13F7041;\n Wed, 30 Dec 2020 23:22:56 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=TZcqjor1jPSuJZ5fyRz4kyV1x/WOcBHyBvln5BnrHH8=;\n b=RepPiZpFQrBcCn3j3n5NxSv+0VIzD7hAs0Nyf7usARJPXyP41Hj/XO8dhBBbNCYpXGOC\n 3z0+uss2ghoi/7dFzV/Qb5ss3EXYOfBfjENnD9l/QEY4ykzdkBIQJjSROpBuXp88UJgi\n SVtiqx5ZsG5XcYRZfrbyGox4Ail4aixAlIqi0PYLhpENwRW6E710oW3yS2YfzFfj36wQ\n QnD6ET1qLLqhQ3CqHoqJXXoP8SpqFeuAoa7nhd70thWX7pzQqqKuf2qUQ6E2cy0Xn/1n\n mJipI+cfPvD4VUaRqC4DOlFC/0KnjMjp8qS2ue9wFxqaoSEPC98gjY5KOAShrvus45gw 4A==", "From": "\"Nalla, Pradeep\" <pnalla@marvell.com>", "To": "\"Nalla, Pradeep\" <pnalla@marvell.com>, Radha Mohan Chintakuntla\n <radhac@marvell.com>, Veerasenareddy Burru <vburru@marvell.com>", "CC": "<jerinj@marvell.com>, <sburla@marvell.com>, <dev@dpdk.org>", "Date": "Thu, 31 Dec 2020 07:22:37 +0000", "Message-ID": "<20201231072247.5719-6-pnalla@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20201231072247.5719-1-pnalla@marvell.com>", "References": "<20201231072247.5719-1-pnalla@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737\n definitions=2020-12-31_02:2020-12-30,\n 2020-12-31 signatures=0", "Subject": "[dpdk-dev] [PATCH 05/15] net/octeontx_ep: Add dev info get and\n configure", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: \"Nalla Pradeep\" <pnalla@marvell.com>\n\nAdd device information get and device configure operations.\n\nSigned-off-by: Nalla Pradeep <pnalla@marvell.com>\n---\n drivers/net/octeontx_ep/otx_ep_common.h | 15 +++++\n drivers/net/octeontx_ep/otx_ep_ethdev.c | 80 +++++++++++++++++++++++++\n drivers/net/octeontx_ep/otx_ep_rxtx.h | 10 ++++\n 3 files changed, 105 insertions(+)\n create mode 100644 drivers/net/octeontx_ep/otx_ep_rxtx.h", "diff": "diff --git a/drivers/net/octeontx_ep/otx_ep_common.h b/drivers/net/octeontx_ep/otx_ep_common.h\nindex f096bec1c0..a56a68bbec 100644\n--- a/drivers/net/octeontx_ep/otx_ep_common.h\n+++ b/drivers/net/octeontx_ep/otx_ep_common.h\n@@ -7,9 +7,12 @@\n #define OTX_EP_MAX_RINGS_PER_VF (8)\n #define OTX_EP_CFG_IO_QUEUES OTX_EP_MAX_RINGS_PER_VF\n #define OTX_EP_64BYTE_INSTR (64)\n+#define OTX_EP_MIN_IQ_DESCRIPTORS (128)\n+#define OTX_EP_MIN_OQ_DESCRIPTORS (128)\n #define OTX_EP_MAX_IQ_DESCRIPTORS (8192)\n #define OTX_EP_MAX_OQ_DESCRIPTORS (8192)\n #define OTX_EP_OQ_BUF_SIZE (2048)\n+#define OTX_EP_MIN_RX_BUF_SIZE (64)\n \n #define OTX_EP_OQ_INFOPTR_MODE (0)\n #define OTX_EP_OQ_REFIL_THRESHOLD (16)\n@@ -112,6 +115,10 @@ struct otx_ep_device {\n \n \tstruct otx_ep_fn_list fn_list;\n \n+\tuint32_t max_tx_queues;\n+\n+\tuint32_t max_rx_queues;\n+\n \t/* SR-IOV info */\n \tstruct otx_ep_sriov_info sriov_info;\n \n@@ -119,5 +126,13 @@ struct otx_ep_device {\n \tconst struct otx_ep_config *conf;\n \n \tint port_configured;\n+\n+\tuint64_t rx_offloads;\n+\tuint64_t tx_offloads;\n };\n+\n+#define OTX_EP_MAX_PKT_SZ 64000U\n+\n+#define OTX_EP_MAX_MAC_ADDRS 1\n+\n #endif /* _OTX_EP_COMMON_H_ */\ndiff --git a/drivers/net/octeontx_ep/otx_ep_ethdev.c b/drivers/net/octeontx_ep/otx_ep_ethdev.c\nindex 7ae9618e72..908bed1f60 100644\n--- a/drivers/net/octeontx_ep/otx_ep_ethdev.c\n+++ b/drivers/net/octeontx_ep/otx_ep_ethdev.c\n@@ -10,8 +10,56 @@\n #include \"otx_ep_common.h\"\n #include \"otx_ep_vf.h\"\n #include \"otx2_ep_vf.h\"\n+#include \"otx_ep_rxtx.h\"\n \n #define OTX_EP_DEV(_eth_dev) ((_eth_dev)->data->dev_private)\n+\n+static const struct rte_eth_desc_lim otx_ep_rx_desc_lim = {\n+\t.nb_max\t\t= OTX_EP_MAX_OQ_DESCRIPTORS,\n+\t.nb_min\t\t= OTX_EP_MIN_OQ_DESCRIPTORS,\n+\t.nb_align\t= OTX_EP_RXD_ALIGN,\n+};\n+\n+static const struct rte_eth_desc_lim otx_ep_tx_desc_lim = {\n+\t.nb_max\t\t= OTX_EP_MAX_IQ_DESCRIPTORS,\n+\t.nb_min\t\t= OTX_EP_MIN_IQ_DESCRIPTORS,\n+\t.nb_align\t= OTX_EP_TXD_ALIGN,\n+};\n+\n+static int\n+otx_ep_dev_info_get(struct rte_eth_dev *eth_dev,\n+\t\t struct rte_eth_dev_info *devinfo)\n+{\n+\tstruct otx_ep_device *otx_epvf;\n+\tstruct rte_pci_device *pdev;\n+\tuint32_t dev_id;\n+\n+\totx_epvf = (struct otx_ep_device *)OTX_EP_DEV(eth_dev);\n+\tpdev = otx_epvf->pdev;\n+\tdev_id = pdev->id.device_id;\n+\n+\tdevinfo->speed_capa = ETH_LINK_SPEED_10G;\n+\tdevinfo->max_rx_queues = otx_epvf->max_rx_queues;\n+\tdevinfo->max_tx_queues = otx_epvf->max_tx_queues;\n+\n+\tdevinfo->min_rx_bufsize = OTX_EP_MIN_RX_BUF_SIZE;\n+\tif (dev_id == PCI_DEVID_OCTEONTX_EP_VF ||\n+\t dev_id == PCI_DEVID_OCTEONTX2_EP_NET_VF ||\n+\t dev_id == PCI_DEVID_98XX_EP_NET_VF) {\n+\t\tdevinfo->max_rx_pktlen = OTX_EP_MAX_PKT_SZ;\n+\t\tdevinfo->rx_offload_capa = DEV_RX_OFFLOAD_JUMBO_FRAME;\n+\t\tdevinfo->rx_offload_capa |= DEV_RX_OFFLOAD_SCATTER;\n+\t\tdevinfo->tx_offload_capa = DEV_TX_OFFLOAD_MULTI_SEGS;\n+\t}\n+\n+\tdevinfo->max_mac_addrs = OTX_EP_MAX_MAC_ADDRS;\n+\n+\tdevinfo->rx_desc_lim = otx_ep_rx_desc_lim;\n+\tdevinfo->tx_desc_lim = otx_ep_tx_desc_lim;\n+\n+\treturn 0;\n+}\n+\n static int\n otx_ep_chip_specific_setup(struct otx_ep_device *otx_epvf)\n {\n@@ -62,6 +110,37 @@ otx_epdev_init(struct otx_ep_device *otx_epvf)\n \treturn -ENOMEM;\n }\n \n+static int\n+otx_ep_dev_configure(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev);\n+\tstruct rte_eth_dev_data *data = eth_dev->data;\n+\tstruct rte_eth_conf *conf = &data->dev_conf;\n+\tstruct rte_eth_rxmode *rxmode = &conf->rxmode;\n+\tstruct rte_eth_txmode *txmode = &conf->txmode;\n+\tuint32_t ethdev_queues;\n+\n+\tethdev_queues = (uint32_t)(otx_epvf->sriov_info.rings_per_vf);\n+\tif (eth_dev->data->nb_rx_queues > ethdev_queues ||\n+\t eth_dev->data->nb_tx_queues > ethdev_queues) {\n+\t\totx_ep_err(\"invalid num queues\\n\");\n+\t\treturn -ENOMEM;\n+\t}\n+\totx_ep_info(\"OTX_EP Device is configured with num_txq %d num_rxq %d\\n\",\n+\t\t eth_dev->data->nb_rx_queues, eth_dev->data->nb_tx_queues);\n+\n+\totx_epvf->port_configured = 1;\n+\totx_epvf->rx_offloads = rxmode->offloads;\n+\totx_epvf->tx_offloads = txmode->offloads;\n+\n+\treturn 0;\n+}\n+\n+/* Define our ethernet definitions */\n+static const struct eth_dev_ops otx_ep_eth_dev_ops = {\n+\t.dev_configure\t\t= otx_ep_dev_configure,\n+\t.dev_infos_get\t\t= otx_ep_dev_info_get,\n+};\n \n static int\n otx_ep_eth_dev_uninit(struct rte_eth_dev *eth_dev)\n@@ -105,6 +184,7 @@ otx_ep_eth_dev_init(struct rte_eth_dev *eth_dev)\n \t}\n \totx_epvf->eth_dev = eth_dev;\n \totx_epvf->port_id = eth_dev->data->port_id;\n+\teth_dev->dev_ops = &otx_ep_eth_dev_ops;\n \teth_dev->data->mac_addrs = rte_zmalloc(\"otx_ep\", RTE_ETHER_ADDR_LEN, 0);\n \tif (eth_dev->data->mac_addrs == NULL) {\n \t\totx_ep_err(\"MAC addresses memory allocation failed\\n\");\ndiff --git a/drivers/net/octeontx_ep/otx_ep_rxtx.h b/drivers/net/octeontx_ep/otx_ep_rxtx.h\nnew file mode 100644\nindex 0000000000..819204a763\n--- /dev/null\n+++ b/drivers/net/octeontx_ep/otx_ep_rxtx.h\n@@ -0,0 +1,10 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#ifndef _OTX_EP_RXTX_H_\n+#define _OTX_EP_RXTX_H_\n+\n+#define OTX_EP_RXD_ALIGN 1\n+#define OTX_EP_TXD_ALIGN 1\n+#endif\n", "prefixes": [ "05/15" ] }