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{
    "id": 85313,
    "url": "http://patches.dpdk.org/api/patches/85313/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1608205475-20067-7-git-send-email-michaelba@nvidia.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1608205475-20067-7-git-send-email-michaelba@nvidia.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1608205475-20067-7-git-send-email-michaelba@nvidia.com",
    "date": "2020-12-17T11:44:24",
    "name": "[06/17] net/mlx5: move ASO CQ creation to common",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "497ef8b60d990e385b089886da012ea84dfa599c",
    "submitter": {
        "id": 1949,
        "url": "http://patches.dpdk.org/api/people/1949/?format=api",
        "name": "Michael Baum",
        "email": "michaelba@nvidia.com"
    },
    "delegate": {
        "id": 3268,
        "url": "http://patches.dpdk.org/api/users/3268/?format=api",
        "username": "rasland",
        "first_name": "Raslan",
        "last_name": "Darawsheh",
        "email": "rasland@nvidia.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1608205475-20067-7-git-send-email-michaelba@nvidia.com/mbox/",
    "series": [
        {
            "id": 14348,
            "url": "http://patches.dpdk.org/api/series/14348/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=14348",
            "date": "2020-12-17T11:44:23",
            "name": "common/mlx5: share DevX resources creations",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/14348/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/85313/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/85313/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 22F75A09F6;\n\tThu, 17 Dec 2020 12:46:50 +0100 (CET)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 56244CA52;\n\tThu, 17 Dec 2020 12:45:08 +0100 (CET)",
            "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id AB804CA24\n for <dev@dpdk.org>; Thu, 17 Dec 2020 12:44:56 +0100 (CET)",
            "from Internal Mail-Server by MTLPINE1 (envelope-from\n michaelba@nvidia.com) with SMTP; 17 Dec 2020 13:44:50 +0200",
            "from nvidia.com (pegasus07.mtr.labs.mlnx [10.210.16.112])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BHBio2V004524;\n Thu, 17 Dec 2020 13:44:50 +0200"
        ],
        "From": "Michael Baum <michaelba@nvidia.com>",
        "To": "dev@dpdk.org",
        "Cc": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>",
        "Date": "Thu, 17 Dec 2020 11:44:24 +0000",
        "Message-Id": "<1608205475-20067-7-git-send-email-michaelba@nvidia.com>",
        "X-Mailer": "git-send-email 1.8.3.1",
        "In-Reply-To": "<1608205475-20067-1-git-send-email-michaelba@nvidia.com>",
        "References": "<1608205475-20067-1-git-send-email-michaelba@nvidia.com>",
        "Subject": "[dpdk-dev] [PATCH 06/17] net/mlx5: move ASO CQ creation to common",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Use common function for ASO CQ creation.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/mlx5.h          |  8 +---\n drivers/net/mlx5/mlx5_flow_age.c | 81 +++++++++-------------------------------\n 2 files changed, 19 insertions(+), 70 deletions(-)",
    "diff": "diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 00ccaee..e02faed 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -463,13 +463,7 @@ struct mlx5_flow_counter_mng {\n struct mlx5_aso_cq {\n \tuint16_t log_desc_n;\n \tuint32_t cq_ci:24;\n-\tstruct mlx5_devx_obj *cq;\n-\tstruct mlx5dv_devx_umem *umem_obj;\n-\tunion {\n-\t\tvolatile void *umem_buf;\n-\t\tvolatile struct mlx5_cqe *cqes;\n-\t};\n-\tvolatile uint32_t *db_rec;\n+\tstruct mlx5_devx_cq cq_obj;\n \tuint64_t errors;\n };\n \ndiff --git a/drivers/net/mlx5/mlx5_flow_age.c b/drivers/net/mlx5/mlx5_flow_age.c\nindex 0ea61be..60a8d2a 100644\n--- a/drivers/net/mlx5/mlx5_flow_age.c\n+++ b/drivers/net/mlx5/mlx5_flow_age.c\n@@ -7,10 +7,12 @@\n \n #include <mlx5_malloc.h>\n #include <mlx5_common_os.h>\n+#include <mlx5_common_devx.h>\n \n #include \"mlx5.h\"\n #include \"mlx5_flow.h\"\n \n+\n /**\n  * Destroy Completion Queue used for ASO access.\n  *\n@@ -20,12 +22,8 @@\n static void\n mlx5_aso_cq_destroy(struct mlx5_aso_cq *cq)\n {\n-\tif (cq->cq)\n-\t\tclaim_zero(mlx5_devx_cmd_destroy(cq->cq));\n-\tif (cq->umem_obj)\n-\t\tclaim_zero(mlx5_glue->devx_umem_dereg(cq->umem_obj));\n-\tif (cq->umem_buf)\n-\t\tmlx5_free((void *)(uintptr_t)cq->umem_buf);\n+\tif (cq->cq_obj.cq)\n+\t\tmlx5_devx_cq_destroy(&cq->cq_obj);\n \tmemset(cq, 0, sizeof(*cq));\n }\n \n@@ -42,60 +40,21 @@\n  *   Socket to use for allocation.\n  * @param[in] uar_page_id\n  *   UAR page ID to use.\n- * @param[in] eqn\n- *   EQ number.\n  *\n  * @return\n  *   0 on success, a negative errno value otherwise and rte_errno is set.\n  */\n static int\n mlx5_aso_cq_create(void *ctx, struct mlx5_aso_cq *cq, uint16_t log_desc_n,\n-\t\t   int socket, int uar_page_id, uint32_t eqn)\n+\t\t   int socket, int uar_page_id)\n {\n-\tstruct mlx5_devx_cq_attr attr = { 0 };\n-\tsize_t pgsize = sysconf(_SC_PAGESIZE);\n-\tuint32_t umem_size;\n-\tuint16_t cq_size = 1 << log_desc_n;\n+\tstruct mlx5_devx_cq_attr attr = {\n+\t\t.uar_page_id = uar_page_id,\n+\t};\n \n \tcq->log_desc_n = log_desc_n;\n-\tumem_size = sizeof(struct mlx5_cqe) * cq_size + sizeof(*cq->db_rec) * 2;\n-\tcq->umem_buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, umem_size,\n-\t\t\t\t   4096, socket);\n-\tif (!cq->umem_buf) {\n-\t\tDRV_LOG(ERR, \"Failed to allocate memory for CQ.\");\n-\t\trte_errno = ENOMEM;\n-\t\treturn -ENOMEM;\n-\t}\n-\tcq->umem_obj = mlx5_glue->devx_umem_reg(ctx,\n-\t\t\t\t\t\t(void *)(uintptr_t)cq->umem_buf,\n-\t\t\t\t\t\tumem_size,\n-\t\t\t\t\t\tIBV_ACCESS_LOCAL_WRITE);\n-\tif (!cq->umem_obj) {\n-\t\tDRV_LOG(ERR, \"Failed to register umem for aso CQ.\");\n-\t\tgoto error;\n-\t}\n-\tattr.q_umem_valid = 1;\n-\tattr.db_umem_valid = 1;\n-\tattr.use_first_only = 0;\n-\tattr.overrun_ignore = 0;\n-\tattr.uar_page_id = uar_page_id;\n-\tattr.q_umem_id = mlx5_os_get_umem_id(cq->umem_obj);\n-\tattr.q_umem_offset = 0;\n-\tattr.db_umem_id = attr.q_umem_id;\n-\tattr.db_umem_offset = sizeof(struct mlx5_cqe) * cq_size;\n-\tattr.eqn = eqn;\n-\tattr.log_cq_size = log_desc_n;\n-\tattr.log_page_size = rte_log2_u32(pgsize);\n-\tcq->cq = mlx5_devx_cmd_create_cq(ctx, &attr);\n-\tif (!cq->cq)\n-\t\tgoto error;\n-\tcq->db_rec = RTE_PTR_ADD(cq->umem_buf, (uintptr_t)attr.db_umem_offset);\n \tcq->cq_ci = 0;\n-\tmemset((void *)(uintptr_t)cq->umem_buf, 0xFF, attr.db_umem_offset);\n-\treturn 0;\n-error:\n-\tmlx5_aso_cq_destroy(cq);\n-\treturn -1;\n+\treturn mlx5_devx_cq_create(ctx, &cq->cq_obj, log_desc_n, &attr, socket);\n }\n \n /**\n@@ -194,8 +153,7 @@\n \t\tmlx5_devx_cmd_destroy(sq->sq);\n \t\tsq->sq = NULL;\n \t}\n-\tif (sq->cq.cq)\n-\t\tmlx5_aso_cq_destroy(&sq->cq);\n+\tmlx5_aso_cq_destroy(&sq->cq);\n \tmlx5_aso_devx_dereg_mr(&sq->mr);\n \tmemset(sq, 0, sizeof(*sq));\n }\n@@ -246,8 +204,6 @@\n  *   User Access Region object.\n  * @param[in] pdn\n  *   Protection Domain number to use.\n- * @param[in] eqn\n- *   EQ number.\n  * @param[in] log_desc_n\n  *   Log of number of descriptors in queue.\n  *\n@@ -257,7 +213,7 @@\n static int\n mlx5_aso_sq_create(void *ctx, struct mlx5_aso_sq *sq, int socket,\n \t\t   struct mlx5dv_devx_uar *uar, uint32_t pdn,\n-\t\t   uint32_t eqn,  uint16_t log_desc_n)\n+\t\t   uint16_t log_desc_n)\n {\n \tstruct mlx5_devx_create_sq_attr attr = { 0 };\n \tstruct mlx5_devx_modify_sq_attr modify_attr = { 0 };\n@@ -271,7 +227,7 @@\n \t\t\t\t sq_desc_n, &sq->mr, socket, pdn))\n \t\treturn -1;\n \tif (mlx5_aso_cq_create(ctx, &sq->cq, log_desc_n, socket,\n-\t\t\t\tmlx5_os_get_devx_uar_page_id(uar), eqn))\n+\t\t\t       mlx5_os_get_devx_uar_page_id(uar)))\n \t\tgoto error;\n \tsq->log_desc_n = log_desc_n;\n \tsq->umem_buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, wq_size +\n@@ -295,7 +251,7 @@\n \tattr.tis_lst_sz = 0;\n \tattr.tis_num = 0;\n \tattr.user_index = 0xFFFF;\n-\tattr.cqn = sq->cq.cq->id;\n+\tattr.cqn = sq->cq.cq_obj.cq->id;\n \twq_attr->uar_page = mlx5_os_get_devx_uar_page_id(uar);\n \twq_attr->pd = pdn;\n \twq_attr->wq_type = MLX5_WQ_TYPE_CYCLIC;\n@@ -347,8 +303,7 @@\n mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh)\n {\n \treturn mlx5_aso_sq_create(sh->ctx, &sh->aso_age_mng->aso_sq, 0,\n-\t\t\t\t  sh->tx_uar, sh->pdn, sh->eqn,\n-\t\t\t\t  MLX5_ASO_QUEUE_LOG_DESC);\n+\t\t\t\t  sh->tx_uar, sh->pdn, MLX5_ASO_QUEUE_LOG_DESC);\n }\n \n /**\n@@ -458,7 +413,7 @@\n \tstruct mlx5_aso_cq *cq = &sq->cq;\n \tuint32_t idx = cq->cq_ci & ((1 << cq->log_desc_n) - 1);\n \tvolatile struct mlx5_err_cqe *cqe =\n-\t\t\t\t(volatile struct mlx5_err_cqe *)&cq->cqes[idx];\n+\t\t\t(volatile struct mlx5_err_cqe *)&cq->cq_obj.cqes[idx];\n \n \tcq->errors++;\n \tidx = rte_be_to_cpu_16(cqe->wqe_counter) & (1u << sq->log_desc_n);\n@@ -571,8 +526,8 @@\n \tdo {\n \t\tidx = next_idx;\n \t\tnext_idx = (cq->cq_ci + 1) & mask;\n-\t\trte_prefetch0(&cq->cqes[next_idx]);\n-\t\tcqe = &cq->cqes[idx];\n+\t\trte_prefetch0(&cq->cq_obj.cqes[next_idx]);\n+\t\tcqe = &cq->cq_obj.cqes[idx];\n \t\tret = check_cqe(cqe, cq_size, cq->cq_ci);\n \t\t/*\n \t\t * Be sure owner read is done before any other cookie field or\n@@ -592,7 +547,7 @@\n \t\tmlx5_aso_age_action_update(sh, i);\n \t\tsq->tail += i;\n \t\trte_io_wmb();\n-\t\tcq->db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);\n+\t\tcq->cq_obj.db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);\n \t}\n \treturn i;\n }\n",
    "prefixes": [
        "06/17"
    ]
}