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GET /api/patches/83908/?format=api
{ "id": 83908, "url": "http://patches.dpdk.org/api/patches/83908/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1605024259-18318-4-git-send-email-viacheslavo@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1605024259-18318-4-git-send-email-viacheslavo@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1605024259-18318-4-git-send-email-viacheslavo@nvidia.com", "date": "2020-11-10T16:04:19", "name": "[4/4] net/mlx5: fix UAR used by ASO queues", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "eb6af792f66abb4a7145c7e931ef804b97fc24b8", "submitter": { "id": 1926, "url": "http://patches.dpdk.org/api/people/1926/?format=api", "name": "Slava Ovsiienko", "email": "viacheslavo@nvidia.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1605024259-18318-4-git-send-email-viacheslavo@nvidia.com/mbox/", "series": [ { "id": 13779, "url": "http://patches.dpdk.org/api/series/13779/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=13779", "date": "2020-11-10T16:04:17", "name": "[1/4] common/mlx5: share UAR allocation routine", "version": 1, "mbox": "http://patches.dpdk.org/series/13779/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/83908/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/83908/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E06EDA04DD;\n\tTue, 10 Nov 2020 17:05:14 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 6D2A65958;\n\tTue, 10 Nov 2020 17:04:34 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 6964937B4\n for <dev@dpdk.org>; Tue, 10 Nov 2020 17:04:28 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n viacheslavo@nvidia.com) with SMTP; 10 Nov 2020 18:04:25 +0200", "from nvidia.com (pegasus12.mtr.labs.mlnx [10.210.17.40])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0AAG4L96012156;\n Tue, 10 Nov 2020 18:04:24 +0200" ], "From": "Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "To": "dev@dpdk.org", "Cc": "rasland@nvidia.com, matan@nvidia.com", "Date": "Tue, 10 Nov 2020 16:04:19 +0000", "Message-Id": "<1605024259-18318-4-git-send-email-viacheslavo@nvidia.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1605024259-18318-1-git-send-email-viacheslavo@nvidia.com>", "References": "<1605024259-18318-1-git-send-email-viacheslavo@nvidia.com>", "Subject": "[dpdk-dev] [PATCH 4/4] net/mlx5: fix UAR used by ASO queues", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The dedicated UAR was allocated for the ASO queues.\nThe shared UAR created for Tx queues can be used instead.\n\nFixes: f935ed4b645a (\"net/mlx5: support flow hit action for aging\")\n\nSigned-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/mlx5.h | 1 -\n drivers/net/mlx5/mlx5_flow_age.c | 22 ++++++++++------------\n 2 files changed, 10 insertions(+), 13 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 7ee63a7..2ad927b 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -513,7 +513,6 @@ struct mlx5_aso_sq {\n \t\tvolatile struct mlx5_aso_wqe *wqes;\n \t};\n \tvolatile uint32_t *db_rec;\n-\tstruct mlx5dv_devx_uar *uar_obj;\n \tvolatile uint64_t *uar_addr;\n \tstruct mlx5_aso_devx_mr mr;\n \tuint16_t pi;\ndiff --git a/drivers/net/mlx5/mlx5_flow_age.c b/drivers/net/mlx5/mlx5_flow_age.c\nindex 636bcda..cea2cf7 100644\n--- a/drivers/net/mlx5/mlx5_flow_age.c\n+++ b/drivers/net/mlx5/mlx5_flow_age.c\n@@ -196,8 +196,6 @@\n \t}\n \tif (sq->cq.cq)\n \t\tmlx5_aso_cq_destroy(&sq->cq);\n-\tif (sq->uar_obj)\n-\t\tmlx5_glue->devx_free_uar(sq->uar_obj);\n \tmlx5_aso_devx_dereg_mr(&sq->mr);\n \tmemset(sq, 0, sizeof(*sq));\n }\n@@ -244,6 +242,8 @@\n * Pointer to SQ to create.\n * @param[in] socket\n * Socket to use for allocation.\n+ * @param[in] uar\n+ * User Access Region object.\n * @param[in] pdn\n * Protection Domain number to use.\n * @param[in] eqn\n@@ -256,7 +256,8 @@\n */\n static int\n mlx5_aso_sq_create(void *ctx, struct mlx5_aso_sq *sq, int socket,\n-\t\t uint32_t pdn, uint32_t eqn, uint16_t log_desc_n)\n+\t\t struct mlx5dv_devx_uar *uar, uint32_t pdn,\n+\t\t uint32_t eqn, uint16_t log_desc_n)\n {\n \tstruct mlx5_devx_create_sq_attr attr = { 0 };\n \tstruct mlx5_devx_modify_sq_attr modify_attr = { 0 };\n@@ -269,11 +270,8 @@\n \tif (mlx5_aso_devx_reg_mr(ctx, (MLX5_ASO_AGE_ACTIONS_PER_POOL / 8) *\n \t\t\t\t sq_desc_n, &sq->mr, socket, pdn))\n \t\treturn -1;\n-\tsq->uar_obj = mlx5_glue->devx_alloc_uar(ctx, 0);\n-\tif (!sq->uar_obj)\n-\t\tgoto error;\n \tif (mlx5_aso_cq_create(ctx, &sq->cq, log_desc_n, socket,\n-\t\t\t\tmlx5_os_get_devx_uar_page_id(sq->uar_obj), eqn))\n+\t\t\t\tmlx5_os_get_devx_uar_page_id(uar), eqn))\n \t\tgoto error;\n \tsq->log_desc_n = log_desc_n;\n \tsq->umem_buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, wq_size +\n@@ -297,7 +295,7 @@\n \tattr.tis_num = 0;\n \tattr.user_index = 0xFFFF;\n \tattr.cqn = sq->cq.cq->id;\n-\twq_attr->uar_page = mlx5_os_get_devx_uar_page_id(sq->uar_obj);\n+\twq_attr->uar_page = mlx5_os_get_devx_uar_page_id(uar);\n \twq_attr->pd = pdn;\n \twq_attr->wq_type = MLX5_WQ_TYPE_CYCLIC;\n \twq_attr->log_wq_pg_sz = rte_log2_u32(pgsize);\n@@ -327,8 +325,7 @@\n \tsq->tail = 0;\n \tsq->sqn = sq->sq->id;\n \tsq->db_rec = RTE_PTR_ADD(sq->umem_buf, (uintptr_t)(wq_attr->dbr_addr));\n-\tsq->uar_addr = (volatile uint64_t *)((uint8_t *)sq->uar_obj->base_addr +\n-\t\t\t\t\t\t\t\t\t 0x800);\n+\tsq->uar_addr = (volatile uint64_t *)((uint8_t *)uar->base_addr + 0x800);\n \tmlx5_aso_init_sq(sq);\n \treturn 0;\n error:\n@@ -348,8 +345,9 @@\n int\n mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh)\n {\n-\treturn mlx5_aso_sq_create(sh->ctx, &sh->aso_age_mng->aso_sq, 0, sh->pdn,\n-\t\t\t\t sh->eqn, MLX5_ASO_QUEUE_LOG_DESC);\n+\treturn mlx5_aso_sq_create(sh->ctx, &sh->aso_age_mng->aso_sq, 0,\n+\t\t\t\t sh->tx_uar, sh->pdn, sh->eqn,\n+\t\t\t\t MLX5_ASO_QUEUE_LOG_DESC);\n }\n \n /**\n", "prefixes": [ "4/4" ] }