get:
Show a patch.

patch:
Update a patch.

put:
Update a patch.

GET /api/patches/83790/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 83790,
    "url": "http://patches.dpdk.org/api/patches/83790/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1604634716-43484-5-git-send-email-oulijun@huawei.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1604634716-43484-5-git-send-email-oulijun@huawei.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1604634716-43484-5-git-send-email-oulijun@huawei.com",
    "date": "2020-11-06T03:51:55",
    "name": "[v2,4/5] net/hns3: check PCI config space writes",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": true,
    "hash": "f6eeb585cada0b20583e71fa632435c6da5d2111",
    "submitter": {
        "id": 1675,
        "url": "http://patches.dpdk.org/api/people/1675/?format=api",
        "name": "Lijun Ou",
        "email": "oulijun@huawei.com"
    },
    "delegate": {
        "id": 319,
        "url": "http://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1604634716-43484-5-git-send-email-oulijun@huawei.com/mbox/",
    "series": [
        {
            "id": 13715,
            "url": "http://patches.dpdk.org/api/series/13715/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=13715",
            "date": "2020-11-06T03:51:51",
            "name": "bugfix and cleanups for hns3",
            "version": 2,
            "mbox": "http://patches.dpdk.org/series/13715/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/83790/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/83790/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 84B1FA0524;\n\tFri,  6 Nov 2020 04:52:41 +0100 (CET)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 698323772;\n\tFri,  6 Nov 2020 04:51:42 +0100 (CET)",
            "from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190])\n by dpdk.org (Postfix) with ESMTP id D7E882C2E\n for <dev@dpdk.org>; Fri,  6 Nov 2020 04:51:39 +0100 (CET)",
            "from DGGEMS407-HUB.china.huawei.com (unknown [172.30.72.58])\n by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4CS5zT3Jh0z15QRJ\n for <dev@dpdk.org>; Fri,  6 Nov 2020 11:51:33 +0800 (CST)",
            "from localhost.localdomain (10.69.192.56) by\n DGGEMS407-HUB.china.huawei.com (10.3.19.207) with Microsoft SMTP Server id\n 14.3.487.0; Fri, 6 Nov 2020 11:51:27 +0800"
        ],
        "From": "Lijun Ou <oulijun@huawei.com>",
        "To": "<ferruh.yigit@intel.com>",
        "CC": "<dev@dpdk.org>, <linuxarm@huawei.com>",
        "Date": "Fri, 6 Nov 2020 11:51:55 +0800",
        "Message-ID": "<1604634716-43484-5-git-send-email-oulijun@huawei.com>",
        "X-Mailer": "git-send-email 2.7.4",
        "In-Reply-To": "<1604634716-43484-1-git-send-email-oulijun@huawei.com>",
        "References": "<1604586194-29523-1-git-send-email-oulijun@huawei.com>\n <1604634716-43484-1-git-send-email-oulijun@huawei.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "X-Originating-IP": "[10.69.192.56]",
        "X-CFilter-Loop": "Reflected",
        "Subject": "[dpdk-dev] [PATCH v2 4/5] net/hns3: check PCI config space writes",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Here adds a check for the return value when calling\nrte_pci_write_config.\n\nCoverity issue: 363714\nFixes: cea37e513329 (\"net/hns3: fix FLR reset\")\nCc: stable@dpdk.org\n\nSigned-off-by: Lijun Ou <oulijun@huawei.com>\n---\nV1->V2:\n- rte_pci_wirte_config -> rte_pci_write_config\n---\n drivers/net/hns3/hns3_ethdev_vf.c | 10 +++++++---\n 1 file changed, 7 insertions(+), 3 deletions(-)",
    "diff": "diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c\nindex 2e9bfda..2f6d91b 100644\n--- a/drivers/net/hns3/hns3_ethdev_vf.c\n+++ b/drivers/net/hns3/hns3_ethdev_vf.c\n@@ -139,7 +139,7 @@ hns3vf_enable_msix(const struct rte_pci_device *device, bool op)\n \t\tret = rte_pci_read_config(device, &control, sizeof(control),\n \t\t\t\t    (pos + PCI_MSIX_FLAGS));\n \t\tif (ret < 0) {\n-\t\t\tPMD_INIT_LOG(ERR, \"Failed to read PCI offset 0x%x\",\n+\t\t\tPMD_INIT_LOG(ERR, \"failed to read PCI offset 0x%x\",\n \t\t\t\t     (pos + PCI_MSIX_FLAGS));\n \t\t\treturn -ENXIO;\n \t\t}\n@@ -148,8 +148,12 @@ hns3vf_enable_msix(const struct rte_pci_device *device, bool op)\n \t\t\tcontrol |= PCI_MSIX_FLAGS_ENABLE;\n \t\telse\n \t\t\tcontrol &= ~PCI_MSIX_FLAGS_ENABLE;\n-\t\trte_pci_write_config(device, &control, sizeof(control),\n-\t\t\t\t     (pos + PCI_MSIX_FLAGS));\n+\t\tret = rte_pci_write_config(device, &control, sizeof(control),\n+\t\t\t\t\t  (pos + PCI_MSIX_FLAGS));\n+\t\tif (ret < 0) {\n+\t\t\tPMD_INIT_LOG(ERR, \"failed to write PCI offset 0x%x\",\n+\t\t\t\t    (pos + PCI_MSIX_FLAGS));\n+\t\t}\n \t\treturn 0;\n \t}\n \treturn -ENXIO;\n",
    "prefixes": [
        "v2",
        "4/5"
    ]
}