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GET /api/patches/8312/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 8312,
    "url": "http://patches.dpdk.org/api/patches/8312/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1446182873-28814-4-git-send-email-cunming.liang@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1446182873-28814-4-git-send-email-cunming.liang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1446182873-28814-4-git-send-email-cunming.liang@intel.com",
    "date": "2015-10-30T05:27:45",
    "name": "[dpdk-dev,v2,03/11] igb: reserve intr vector zero for misc cause",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "c4a802813d44e9facb82786ed6ed76fd541c67af",
    "submitter": {
        "id": 46,
        "url": "http://patches.dpdk.org/api/people/46/?format=api",
        "name": "Cunming Liang",
        "email": "cunming.liang@intel.com"
    },
    "delegate": null,
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1446182873-28814-4-git-send-email-cunming.liang@intel.com/mbox/",
    "series": [],
    "comments": "http://patches.dpdk.org/api/patches/8312/comments/",
    "check": "pending",
    "checks": "http://patches.dpdk.org/api/patches/8312/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id ABF848E70;\n\tFri, 30 Oct 2015 06:28:19 +0100 (CET)",
            "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby dpdk.org (Postfix) with ESMTP id C9C0B8DED\n\tfor <dev@dpdk.org>; Fri, 30 Oct 2015 06:28:13 +0100 (CET)",
            "from orsmga003.jf.intel.com ([10.7.209.27])\n\tby fmsmga102.fm.intel.com with ESMTP; 29 Oct 2015 22:28:14 -0700",
            "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby orsmga003.jf.intel.com with ESMTP; 29 Oct 2015 22:28:13 -0700",
            "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id t9U5S67R023322;\n\tFri, 30 Oct 2015 13:28:06 +0800",
            "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid t9U5S3oV028884; Fri, 30 Oct 2015 13:28:05 +0800",
            "(from cliang18@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id t9U5S3XT028880; \n\tFri, 30 Oct 2015 13:28:03 +0800"
        ],
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.20,217,1444719600\"; d=\"scan'208\";a=\"674833202\"",
        "From": "Cunming Liang <cunming.liang@intel.com>",
        "To": "dev@dpdk.org",
        "Date": "Fri, 30 Oct 2015 13:27:45 +0800",
        "Message-Id": "<1446182873-28814-4-git-send-email-cunming.liang@intel.com>",
        "X-Mailer": "git-send-email 1.7.4.1",
        "In-Reply-To": "<1446182873-28814-1-git-send-email-cunming.liang@intel.com>",
        "References": "<1443072831-19065-1-git-send-email-cunming.liang@intel.com>\n\t<1446182873-28814-1-git-send-email-cunming.liang@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v2 03/11] igb: reserve intr vector zero for misc\n\tcause",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "According to the VFIO interrupt mapping, the interrupt vector id for rxq starts from RX_VEC_START.\nIt doesn't impact the UIO cases.\n\nSigned-off-by: Cunming Liang <cunming.liang@intel.com>\n---\n drivers/net/e1000/igb_ethdev.c | 19 ++++++++++++++-----\n 1 file changed, 14 insertions(+), 5 deletions(-)",
    "diff": "diff --git a/drivers/net/e1000/igb_ethdev.c b/drivers/net/e1000/igb_ethdev.c\nindex 3ab082e..b3a802f 100644\n--- a/drivers/net/e1000/igb_ethdev.c\n+++ b/drivers/net/e1000/igb_ethdev.c\n@@ -4213,7 +4213,10 @@ eth_igb_configure_msix_intr(struct rte_eth_dev *dev)\n \tuint32_t tmpval, regval, intr_mask;\n \tstruct e1000_hw *hw =\n \t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n-\tuint32_t vec = 0;\n+\tuint32_t vec = MISC_VEC_ID;\n+\tuint32_t base = MISC_VEC_ID;\n+\tuint32_t misc_shift = 0;\n+\n \tstruct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;\n \n \t/* won't configure msix register if no mapping is done\n@@ -4222,6 +4225,11 @@ eth_igb_configure_msix_intr(struct rte_eth_dev *dev)\n \tif (!rte_intr_dp_is_en(intr_handle))\n \t\treturn;\n \n+\tif (rte_intr_allow_others(intr_handle)) {\n+\t\tvec = base = RX_VEC_START;\n+\t\tmisc_shift = 1;\n+\t}\n+\n \t/* set interrupt vector for other causes */\n \tif (hw->mac.type == e1000_82575) {\n \t\ttmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);\n@@ -4250,8 +4258,8 @@ eth_igb_configure_msix_intr(struct rte_eth_dev *dev)\n \t\tE1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |\n \t\t\t\t\tE1000_GPIE_PBA | E1000_GPIE_EIAME |\n \t\t\t\t\tE1000_GPIE_NSICR);\n-\n-\t\tintr_mask = (1 << intr_handle->max_intr) - 1;\n+\t\tintr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<\n+\t\t\tmisc_shift;\n \t\tregval = E1000_READ_REG(hw, E1000_EIAC);\n \t\tE1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);\n \n@@ -4265,14 +4273,15 @@ eth_igb_configure_msix_intr(struct rte_eth_dev *dev)\n \t/* use EIAM to auto-mask when MSI-X interrupt\n \t * is asserted, this saves a register write for every interrupt\n \t */\n-\tintr_mask = (1 << intr_handle->nb_efd) - 1;\n+\tintr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<\n+\t\tmisc_shift;\n \tregval = E1000_READ_REG(hw, E1000_EIAM);\n \tE1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);\n \n \tfor (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {\n \t\teth_igb_assign_msix_vector(hw, 0, queue_id, vec);\n \t\tintr_handle->intr_vec[queue_id] = vec;\n-\t\tif (vec < intr_handle->nb_efd - 1)\n+\t\tif (vec < base + intr_handle->nb_efd - 1)\n \t\t\tvec++;\n \t}\n \n",
    "prefixes": [
        "dpdk-dev",
        "v2",
        "03/11"
    ]
}