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GET /api/patches/82755/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 82755,
    "url": "http://patches.dpdk.org/api/patches/82755/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1603975751-27955-8-git-send-email-oulijun@huawei.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1603975751-27955-8-git-send-email-oulijun@huawei.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1603975751-27955-8-git-send-email-oulijun@huawei.com",
    "date": "2020-10-29T12:49:10",
    "name": "[v2,7/8] net/hns3: fix HW ring not clear after queue stop",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "8093fdcd3d5dfec986398396bd041bc96da5ff41",
    "submitter": {
        "id": 1675,
        "url": "http://patches.dpdk.org/api/people/1675/?format=api",
        "name": "Lijun Ou",
        "email": "oulijun@huawei.com"
    },
    "delegate": {
        "id": 319,
        "url": "http://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1603975751-27955-8-git-send-email-oulijun@huawei.com/mbox/",
    "series": [
        {
            "id": 13461,
            "url": "http://patches.dpdk.org/api/series/13461/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=13461",
            "date": "2020-10-29T12:49:08",
            "name": "[v2,1/8] net/hns3: enable RSS for ipv6-sctp dst/src port fields",
            "version": 2,
            "mbox": "http://patches.dpdk.org/series/13461/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/82755/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/82755/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B0C17A04B5;\n\tThu, 29 Oct 2020 13:50:32 +0100 (CET)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 203FFCC48;\n\tThu, 29 Oct 2020 13:49:04 +0100 (CET)",
            "from szxga07-in.huawei.com (szxga07-in.huawei.com [45.249.212.35])\n by dpdk.org (Postfix) with ESMTP id 7A59ACB79\n for <dev@dpdk.org>; Thu, 29 Oct 2020 13:48:52 +0100 (CET)",
            "from DGGEMS404-HUB.china.huawei.com (unknown [172.30.72.60])\n by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4CMQH41yzdz70Kr\n for <dev@dpdk.org>; Thu, 29 Oct 2020 20:48:48 +0800 (CST)",
            "from localhost.localdomain (10.69.192.56) by\n DGGEMS404-HUB.china.huawei.com (10.3.19.204) with Microsoft SMTP Server id\n 14.3.487.0; Thu, 29 Oct 2020 20:48:37 +0800"
        ],
        "From": "Lijun Ou <oulijun@huawei.com>",
        "To": "<ferruh.yigit@intel.com>",
        "CC": "<dev@dpdk.org>, <linuxarm@huawei.com>",
        "Date": "Thu, 29 Oct 2020 20:49:10 +0800",
        "Message-ID": "<1603975751-27955-8-git-send-email-oulijun@huawei.com>",
        "X-Mailer": "git-send-email 2.7.4",
        "In-Reply-To": "<1603975751-27955-1-git-send-email-oulijun@huawei.com>",
        "References": "<1603973875-8431-1-git-send-email-oulijun@huawei.com>\n <1603975751-27955-1-git-send-email-oulijun@huawei.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "X-Originating-IP": "[10.69.192.56]",
        "X-CFilter-Loop": "Reflected",
        "Subject": "[dpdk-dev] [PATCH v2 7/8] net/hns3: fix HW ring not clear after\n\tqueue stop",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Chengchang Tang <tangchengchang@huawei.com>\n\nCurrently, the rx HW ring is not cleared after queue stop.\nWhen there are packets remaining in the HW rings and the\nqueues have been stopped, if upper layer user calls the\nrx_burst function at this time, an illegal memory access\nwill occur due to the sw rings has been released.\n\nThis patch fix this by reset the sw ring after disable the\nqueue.\n\nFixes: fa29fe45a7b4 (\"net/hns3: support queue start and stop\")\nCc: stable@dpdk.org\n\nSigned-off-by: Chengchang Tang <tangchengchang@huawei.com>\nSigned-off-by: Lijun Ou <oulijun@huawei.com>\n---\n drivers/net/hns3/hns3_rxtx.c | 16 ++++++++++++++++\n 1 file changed, 16 insertions(+)",
    "diff": "diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c\nindex 3386453..2988a4b 100644\n--- a/drivers/net/hns3/hns3_rxtx.c\n+++ b/drivers/net/hns3/hns3_rxtx.c\n@@ -3805,6 +3805,19 @@ hns3_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n \treturn ret;\n }\n \n+static void\n+hns3_reset_sw_rxq(struct hns3_rx_queue *rxq)\n+{\n+\trxq->next_to_use = 0;\n+\trxq->rx_rearm_start = 0;\n+\trxq->rx_free_hold = 0;\n+\trxq->rx_rearm_nb = 0;\n+\trxq->pkt_first_seg = NULL;\n+\trxq->pkt_last_seg = NULL;\n+\tmemset(&rxq->rx_ring[0], 0, rxq->nb_rx_desc * sizeof(struct hns3_desc));\n+\thns3_rxq_vec_setup(rxq);\n+}\n+\n int\n hns3_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n {\n@@ -3815,7 +3828,10 @@ hns3_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n \t\treturn -ENOTSUP;\n \n \thns3_enable_rxq(rxq, false);\n+\n \thns3_rx_queue_release_mbufs(rxq);\n+\n+\thns3_reset_sw_rxq(rxq);\n \tdev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;\n \n \treturn 0;\n",
    "prefixes": [
        "v2",
        "7/8"
    ]
}