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GET /api/patches/81892/?format=api
{ "id": 81892, "url": "http://patches.dpdk.org/api/patches/81892/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1603437295-119083-25-git-send-email-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1603437295-119083-25-git-send-email-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1603437295-119083-25-git-send-email-suanmingm@nvidia.com", "date": "2020-10-23T07:14:54", "name": "[v2,24/25] net/mlx5: make port ID action cache thread safe", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "81bae6c0e82a2eafd0f6bba291461a7b7fd22763", "submitter": { "id": 1887, "url": "http://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1603437295-119083-25-git-send-email-suanmingm@nvidia.com/mbox/", "series": [ { "id": 13250, "url": "http://patches.dpdk.org/api/series/13250/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=13250", "date": "2020-10-23T07:14:30", "name": "*net/mlx5: support multiple-thread flow operations", "version": 2, "mbox": "http://patches.dpdk.org/series/13250/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/81892/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/81892/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7F097A04DE;\n\tFri, 23 Oct 2020 09:24:22 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 0C0E1A960;\n\tFri, 23 Oct 2020 09:17:17 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id A05DCA8FB\n for <dev@dpdk.org>; Fri, 23 Oct 2020 09:15:54 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n suanmingm@nvidia.com) with SMTP; 23 Oct 2020 10:15:48 +0300", "from nvidia.com (mtbc-r640-04.mtbc.labs.mlnx [10.75.70.9])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 09N7F2Lh026736;\n Fri, 23 Oct 2020 10:15:47 +0300" ], "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "Matan Azrad <matan@nvidia.com>, Shahaf Shuler <shahafs@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "Cc": "dev@dpdk.org, Xueming Li <xuemingl@nvidia.com>", "Date": "Fri, 23 Oct 2020 15:14:54 +0800", "Message-Id": "<1603437295-119083-25-git-send-email-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1603437295-119083-1-git-send-email-suanmingm@nvidia.com>", "References": "<1601984948-313027-1-git-send-email-suanmingm@nvidia.com>\n <1603437295-119083-1-git-send-email-suanmingm@nvidia.com>", "Subject": "[dpdk-dev] [PATCH v2 24/25] net/mlx5: make port ID action cache\n\tthread safe", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Xueming Li <xuemingl@nvidia.com>\n\nTo support multi-thread flow insertion, this patch convert port id\naction cache list to thread safe cache list.\n\nSigned-off-by: Xueming Li <xuemingl@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_os.c | 7 ++\n drivers/net/mlx5/mlx5.h | 2 +-\n drivers/net/mlx5/mlx5_flow.h | 15 +++--\n drivers/net/mlx5/mlx5_flow_dv.c | 141 +++++++++++++++++++++------------------\n 4 files changed, 94 insertions(+), 71 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex b0dcb40..4e56ded 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -236,6 +236,12 @@\n \t\tgoto error;\n \t/* The resources below are only valid with DV support. */\n #ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+\t/* Init port id action cache list. */\n+\tsnprintf(s, sizeof(s), \"%s_port_id_action_cache\", sh->ibdev_name);\n+\tmlx5_cache_list_init(&sh->port_id_action_list, s, 0, sh,\n+\t\t\t flow_dv_port_id_create_cb,\n+\t\t\t flow_dv_port_id_match_cb,\n+\t\t\t flow_dv_port_id_remove_cb);\n \t/* Create tags hash list table. */\n \tsnprintf(s, sizeof(s), \"%s_tags\", sh->ibdev_name);\n \tsh->tag_table = mlx5_hlist_create(s, MLX5_TAGS_HLIST_ARRAY_SIZE, 0,\n@@ -417,6 +423,7 @@\n \t\tmlx5_hlist_destroy(sh->tag_table);\n \t\tsh->tag_table = NULL;\n \t}\n+\tmlx5_cache_list_destroy(&sh->port_id_action_list);\n \tmlx5_free_table_hash_list(priv);\n }\n \ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 30ab09b..60a9ab9 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -646,7 +646,7 @@ struct mlx5_dev_ctx_shared {\n \tstruct mlx5_hlist *encaps_decaps; /* Encap/decap action hash list. */\n \tstruct mlx5_hlist *modify_cmds;\n \tstruct mlx5_hlist *tag_table;\n-\tuint32_t port_id_action_list; /* List of port ID actions. */\n+\tstruct mlx5_cache_list port_id_action_list; /* Port ID action cache. */\n \tuint32_t push_vlan_action_list; /* List of push VLAN actions. */\n \tuint32_t sample_action_list; /* List of sample actions. */\n \tuint32_t dest_array_list; /* List of destination array actions. */\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex eac8916..dbbbcd1 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -482,12 +482,10 @@ struct mlx5_flow_dv_jump_tbl_resource {\n \n /* Port ID resource structure. */\n struct mlx5_flow_dv_port_id_action_resource {\n-\tILIST_ENTRY(uint32_t)next;\n-\t/* Pointer to next element. */\n-\trte_atomic32_t refcnt; /**< Reference counter. */\n-\tvoid *action;\n-\t/**< Action object. */\n+\tstruct mlx5_cache_entry entry;\n+\tvoid *action; /**< Action object. */\n \tuint32_t port_id; /**< Port ID value. */\n+\tuint32_t idx; /**< Indexed pool memory index. */\n };\n \n /* Push VLAN action resource structure */\n@@ -1177,4 +1175,11 @@ struct mlx5_cache_entry *flow_dv_matcher_create_cb(struct mlx5_cache_list *list,\n void flow_dv_matcher_remove_cb(struct mlx5_cache_list *list,\n \t\t\t struct mlx5_cache_entry *entry);\n \n+int flow_dv_port_id_match_cb(struct mlx5_cache_list *list,\n+\t\t\t struct mlx5_cache_entry *entry, void *cb_ctx);\n+struct mlx5_cache_entry *flow_dv_port_id_create_cb(struct mlx5_cache_list *list,\n+\t\tstruct mlx5_cache_entry *entry, void *cb_ctx);\n+void flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,\n+\t\t\t struct mlx5_cache_entry *entry);\n+\n #endif /* RTE_PMD_MLX5_FLOW_H_ */\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 2d0ef3a..9fa902a 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -2960,6 +2960,52 @@ struct mlx5_hlist_entry *\n \treturn 0;\n }\n \n+int\n+flow_dv_port_id_match_cb(struct mlx5_cache_list *list __rte_unused,\n+\t\t\t struct mlx5_cache_entry *entry, void *cb_ctx)\n+{\n+\tstruct mlx5_flow_cb_ctx *ctx = cb_ctx;\n+\tstruct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;\n+\tstruct mlx5_flow_dv_port_id_action_resource *res =\n+\t\t\tcontainer_of(entry, typeof(*res), entry);\n+\n+\treturn ref->port_id != res->port_id;\n+}\n+\n+struct mlx5_cache_entry *\n+flow_dv_port_id_create_cb(struct mlx5_cache_list *list,\n+\t\t\t struct mlx5_cache_entry *entry __rte_unused,\n+\t\t\t void *cb_ctx)\n+{\n+\tstruct mlx5_dev_ctx_shared *sh = list->ctx;\n+\tstruct mlx5_flow_cb_ctx *ctx = cb_ctx;\n+\tstruct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;\n+\tstruct mlx5_flow_dv_port_id_action_resource *cache;\n+\tuint32_t idx;\n+\tint ret;\n+\n+\t/* Register new port id action resource. */\n+\tcache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);\n+\tif (!cache) {\n+\t\trte_flow_error_set(ctx->error, ENOMEM,\n+\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,\n+\t\t\t\t \"cannot allocate port_id action cache memory\");\n+\t\treturn NULL;\n+\t}\n+\t*cache = *ref;\n+\tret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,\n+\t\t\t\t\t\t\tref->port_id,\n+\t\t\t\t\t\t\t&cache->action);\n+\tif (ret) {\n+\t\tmlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);\n+\t\trte_flow_error_set(ctx->error, ENOMEM,\n+\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,\n+\t\t\t\t \"cannot create action\");\n+\t\treturn NULL;\n+\t}\n+\treturn &cache->entry;\n+}\n+\n /**\n * Find existing table port ID resource or create and register a new one.\n *\n@@ -2983,51 +3029,19 @@ struct mlx5_hlist_entry *\n \t\t\t struct rte_flow_error *error)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_dev_ctx_shared *sh = priv->sh;\n-\tstruct mlx5_flow_dv_port_id_action_resource *cache_resource;\n-\tuint32_t idx = 0;\n-\tint ret;\n+\tstruct mlx5_cache_entry *entry;\n+\tstruct mlx5_flow_dv_port_id_action_resource *cache;\n+\tstruct mlx5_flow_cb_ctx ctx = {\n+\t\t.error = error,\n+\t\t.data = resource,\n+\t};\n \n-\t/* Lookup a matching resource from cache. */\n-\tILIST_FOREACH(sh->ipool[MLX5_IPOOL_PORT_ID], sh->port_id_action_list,\n-\t\t idx, cache_resource, next) {\n-\t\tif (resource->port_id == cache_resource->port_id) {\n-\t\t\tDRV_LOG(DEBUG, \"port id action resource resource %p: \"\n-\t\t\t\t\"refcnt %d++\",\n-\t\t\t\t(void *)cache_resource,\n-\t\t\t\trte_atomic32_read(&cache_resource->refcnt));\n-\t\t\trte_atomic32_inc(&cache_resource->refcnt);\n-\t\t\tdev_flow->handle->rix_port_id_action = idx;\n-\t\t\tdev_flow->dv.port_id_action = cache_resource;\n-\t\t\treturn 0;\n-\t\t}\n-\t}\n-\t/* Register new port id action resource. */\n-\tcache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID],\n-\t\t\t\t &dev_flow->handle->rix_port_id_action);\n-\tif (!cache_resource)\n-\t\treturn rte_flow_error_set(error, ENOMEM,\n-\t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,\n-\t\t\t\t\t \"cannot allocate resource memory\");\n-\t*cache_resource = *resource;\n-\tret = mlx5_flow_os_create_flow_action_dest_port\n-\t\t\t\t(priv->sh->fdb_domain, resource->port_id,\n-\t\t\t\t &cache_resource->action);\n-\tif (ret) {\n-\t\tmlx5_free(cache_resource);\n-\t\treturn rte_flow_error_set(error, ENOMEM,\n-\t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n-\t\t\t\t\t NULL, \"cannot create action\");\n-\t}\n-\trte_atomic32_init(&cache_resource->refcnt);\n-\trte_atomic32_inc(&cache_resource->refcnt);\n-\tILIST_INSERT(sh->ipool[MLX5_IPOOL_PORT_ID], &sh->port_id_action_list,\n-\t\t dev_flow->handle->rix_port_id_action, cache_resource,\n-\t\t next);\n-\tdev_flow->dv.port_id_action = cache_resource;\n-\tDRV_LOG(DEBUG, \"new port id action resource %p: refcnt %d++\",\n-\t\t(void *)cache_resource,\n-\t\trte_atomic32_read(&cache_resource->refcnt));\n+\tentry = mlx5_cache_register(&priv->sh->port_id_action_list, &ctx);\n+\tif (!entry)\n+\t\treturn -rte_errno;\n+\tcache = container_of(entry, typeof(*cache), entry);\n+\tdev_flow->dv.port_id_action = cache;\n+\tdev_flow->handle->rix_port_id_action = cache->idx;\n \treturn 0;\n }\n \n@@ -10159,6 +10173,18 @@ struct mlx5_hlist_entry *\n \treturn mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);\n }\n \n+void\n+flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,\n+\t\t\t struct mlx5_cache_entry *entry)\n+{\n+\tstruct mlx5_dev_ctx_shared *sh = list->ctx;\n+\tstruct mlx5_flow_dv_port_id_action_resource *cache =\n+\t\t\tcontainer_of(entry, typeof(*cache), entry);\n+\n+\tclaim_zero(mlx5_flow_os_destroy_flow_action(cache->action));\n+\tmlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], cache->idx);\n+}\n+\n /**\n * Release port ID action resource.\n *\n@@ -10175,29 +10201,14 @@ struct mlx5_hlist_entry *\n \t\t\t\t\tuint32_t port_id)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_flow_dv_port_id_action_resource *cache_resource;\n-\tuint32_t idx = port_id;\n+\tstruct mlx5_flow_dv_port_id_action_resource *cache;\n \n-\tcache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID],\n-\t\t\t\t\tidx);\n-\tif (!cache_resource)\n+\tcache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);\n+\tif (!cache)\n \t\treturn 0;\n-\tMLX5_ASSERT(cache_resource->action);\n-\tDRV_LOG(DEBUG, \"port ID action resource %p: refcnt %d--\",\n-\t\t(void *)cache_resource,\n-\t\trte_atomic32_read(&cache_resource->refcnt));\n-\tif (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {\n-\t\tclaim_zero(mlx5_flow_os_destroy_flow_action\n-\t\t\t\t\t\t(cache_resource->action));\n-\t\tILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PORT_ID],\n-\t\t\t &priv->sh->port_id_action_list, idx,\n-\t\t\t cache_resource, next);\n-\t\tmlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PORT_ID], idx);\n-\t\tDRV_LOG(DEBUG, \"port id action resource %p: removed\",\n-\t\t\t(void *)cache_resource);\n-\t\treturn 0;\n-\t}\n-\treturn 1;\n+\tMLX5_ASSERT(cache->action);\n+\treturn mlx5_cache_unregister(&priv->sh->port_id_action_list,\n+\t\t\t\t &cache->entry);\n }\n \n /**\n", "prefixes": [ "v2", "24/25" ] }