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GET /api/patches/81337/?format=api
{ "id": 81337, "url": "http://patches.dpdk.org/api/patches/81337/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20201019085415.82207-54-jiawenwu@trustnetic.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201019085415.82207-54-jiawenwu@trustnetic.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201019085415.82207-54-jiawenwu@trustnetic.com", "date": "2020-10-19T08:54:10", "name": "[v4,53/58] net/txgbe: add mirror rule operations", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "f50383af0beb6369785abfbb05c2380a046c8baa", "submitter": { "id": 1932, "url": "http://patches.dpdk.org/api/people/1932/?format=api", "name": "Jiawen Wu", "email": "jiawenwu@trustnetic.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20201019085415.82207-54-jiawenwu@trustnetic.com/mbox/", "series": [ { "id": 13094, "url": "http://patches.dpdk.org/api/series/13094/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=13094", "date": "2020-10-19T08:53:17", "name": "net: txgbe PMD", "version": 4, "mbox": "http://patches.dpdk.org/series/13094/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/81337/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/81337/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 93129A04DC;\n\tMon, 19 Oct 2020 11:14:36 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 352E3E2DE;\n\tMon, 19 Oct 2020 10:54:19 +0200 (CEST)", "from qq.com (smtpbg440.qq.com [183.3.255.59])\n by dpdk.org (Postfix) with ESMTP id 5CD69CF8D\n for <dev@dpdk.org>; Mon, 19 Oct 2020 10:53:40 +0200 (CEST)", "from localhost.localdomain.com (unknown [183.129.236.74])\n by esmtp6.qq.com (ESMTP) with\n id ; Mon, 19 Oct 2020 16:53:35 +0800 (CST)" ], "X-QQ-mid": "bizesmtp6t1603097615tm6ihnvg9", "X-QQ-SSF": "01400000002000C0C000B00A0000000", "X-QQ-FEAT": "lm51M56XDGzXBAZmEz1LOi2uZGqJbGpCPNkn/LKJgeFUFgSXbxHZbSJAjI7lM\n D63TtKUg7P77IOZ+P/a1nnJzHrbeqmjyVcEkVo7b8B6i79uGYJG7cRosRgWgaDtvJGsp4lg\n 6W7plzmVnkTN6s2ZHOxo49xqU558HHUsjshFfj1lTK2FszanNE1BX6LVASXrvHaSXOcfg/G\n ZloYKkcO9CFmBJdtKHZeS68jfell6937iBSY+xIKZGQclqkLm72y4ZMx599t9mlKvatd8t7\n vryJjoA7Q87Ev6kWf4VxLEcAthWXjvwyH1zqdvJdf+zwPlW059hUzhLFXxJvMxyJSXXMRsl\n 8IM5BKvSdX/utcTftIEIWECev4TtA==", "X-QQ-GoodBg": "2", "From": "Jiawen Wu <jiawenwu@trustnetic.com>", "To": "dev@dpdk.org", "Cc": "Jiawen Wu <jiawenwu@trustnetic.com>", "Date": "Mon, 19 Oct 2020 16:54:10 +0800", "Message-Id": "<20201019085415.82207-54-jiawenwu@trustnetic.com>", "X-Mailer": "git-send-email 2.18.4", "In-Reply-To": "<20201019085415.82207-1-jiawenwu@trustnetic.com>", "References": "<20201019085415.82207-1-jiawenwu@trustnetic.com>", "X-QQ-SENDSIZE": "520", "Feedback-ID": "bizesmtp:trustnetic.com:qybgweb:qybgweb10", "Subject": "[dpdk-dev] [PATCH v4 53/58] net/txgbe: add mirror rule operations", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add mirror rule set and reset operations.\n\nSigned-off-by: Jiawen Wu <jiawenwu@trustnetic.com>\n---\n doc/guides/nics/features/txgbe.ini | 1 +\n drivers/net/txgbe/txgbe_ethdev.c | 186 +++++++++++++++++++++++++++++\n drivers/net/txgbe/txgbe_ethdev.h | 1 +\n 3 files changed, 188 insertions(+)", "diff": "diff --git a/doc/guides/nics/features/txgbe.ini b/doc/guides/nics/features/txgbe.ini\nindex 20a02706c..a57a1f04f 100644\n--- a/doc/guides/nics/features/txgbe.ini\n+++ b/doc/guides/nics/features/txgbe.ini\n@@ -27,6 +27,7 @@ DCB = Y\n VLAN filter = Y\n Flow control = Y\n Rate limitation = Y\n+Traffic mirroring = Y\n CRC offload = P\n VLAN offload = P\n QinQ offload = P\ndiff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c\nindex de5523860..cc15b470c 100644\n--- a/drivers/net/txgbe/txgbe_ethdev.c\n+++ b/drivers/net/txgbe/txgbe_ethdev.c\n@@ -3172,6 +3172,21 @@ txgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)\n \treturn 0;\n }\n \n+int\n+txgbe_vt_check(struct txgbe_hw *hw)\n+{\n+\tuint32_t reg_val;\n+\n+\t/* if Virtualization Technology is enabled */\n+\treg_val = rd32(hw, TXGBE_PORTCTL);\n+\tif (!(reg_val & TXGBE_PORTCTL_NUMVT_MASK)) {\n+\t\tPMD_INIT_LOG(ERR, \"VT must be enabled for this setting\");\n+\t\treturn -1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n static uint32_t\n txgbe_uta_vector(struct txgbe_hw *hw, struct rte_ether_addr *uc_addr)\n {\n@@ -3309,6 +3324,175 @@ txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)\n \treturn new_val;\n }\n \n+#define TXGBE_INVALID_MIRROR_TYPE(mirror_type) \\\n+\t((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \\\n+\tETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))\n+\n+static int\n+txgbe_mirror_rule_set(struct rte_eth_dev *dev,\n+\t\t struct rte_eth_mirror_conf *mirror_conf,\n+\t\t uint8_t rule_id, uint8_t on)\n+{\n+\tuint32_t mr_ctl, vlvf;\n+\tuint32_t mp_lsb = 0;\n+\tuint32_t mv_msb = 0;\n+\tuint32_t mv_lsb = 0;\n+\tuint32_t mp_msb = 0;\n+\tuint8_t i = 0;\n+\tint reg_index = 0;\n+\tuint64_t vlan_mask = 0;\n+\n+\tconst uint8_t pool_mask_offset = 32;\n+\tconst uint8_t vlan_mask_offset = 32;\n+\tconst uint8_t dst_pool_offset = 8;\n+\tconst uint8_t rule_mr_offset = 4;\n+\tconst uint8_t mirror_rule_mask = 0x0F;\n+\n+\tstruct txgbe_mirror_info *mr_info = TXGBE_DEV_MR_INFO(dev);\n+\tstruct rte_eth_mirror_conf *mr_conf = &mr_info->mr_conf[rule_id];\n+\tstruct txgbe_hw *hw = TXGBE_DEV_HW(dev);\n+\tuint8_t mirror_type = 0;\n+\n+\tif (txgbe_vt_check(hw) < 0)\n+\t\treturn -ENOTSUP;\n+\n+\tif (rule_id >= TXGBE_MAX_MIRROR_RULES)\n+\t\treturn -EINVAL;\n+\n+\tif (TXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {\n+\t\tPMD_DRV_LOG(ERR, \"unsupported mirror type 0x%x.\",\n+\t\t\t mirror_conf->rule_type);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (mirror_conf->rule_type & ETH_MIRROR_VLAN) {\n+\t\tmirror_type |= TXGBE_MIRRCTL_VLAN;\n+\t\t/* Check if vlan id is valid and find conresponding VLAN ID\n+\t\t * index in PSRVLAN\n+\t\t */\n+\t\tfor (i = 0; i < TXGBE_NUM_POOL; i++) {\n+\t\t\tif (mirror_conf->vlan.vlan_mask & (1ULL << i)) {\n+\t\t\t\t/* search vlan id related pool vlan filter\n+\t\t\t\t * index\n+\t\t\t\t */\n+\t\t\t\treg_index = txgbe_find_vlvf_slot(hw,\n+\t\t\t\t\t\tmirror_conf->vlan.vlan_id[i],\n+\t\t\t\t\t\tfalse);\n+\t\t\t\tif (reg_index < 0)\n+\t\t\t\t\treturn -EINVAL;\n+\t\t\t\twr32(hw, TXGBE_PSRVLANIDX, reg_index);\n+\t\t\t\tvlvf = rd32(hw, TXGBE_PSRVLAN);\n+\t\t\t\tif ((TXGBE_PSRVLAN_VID(vlvf) ==\n+\t\t\t\t mirror_conf->vlan.vlan_id[i]))\n+\t\t\t\t\tvlan_mask |= (1ULL << reg_index);\n+\t\t\t\telse\n+\t\t\t\t\treturn -EINVAL;\n+\t\t\t}\n+\t\t}\n+\n+\t\tif (on) {\n+\t\t\tmv_lsb = vlan_mask & BIT_MASK32;\n+\t\t\tmv_msb = vlan_mask >> vlan_mask_offset;\n+\n+\t\t\tmr_conf->vlan.vlan_mask = mirror_conf->vlan.vlan_mask;\n+\t\t\tfor (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {\n+\t\t\t\tif (mirror_conf->vlan.vlan_mask & (1ULL << i))\n+\t\t\t\t\tmr_conf->vlan.vlan_id[i] =\n+\t\t\t\t\t\tmirror_conf->vlan.vlan_id[i];\n+\t\t\t}\n+\t\t} else {\n+\t\t\tmv_lsb = 0;\n+\t\t\tmv_msb = 0;\n+\t\t\tmr_conf->vlan.vlan_mask = 0;\n+\t\t\tfor (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)\n+\t\t\t\tmr_conf->vlan.vlan_id[i] = 0;\n+\t\t}\n+\t}\n+\n+\tif (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {\n+\t\tmirror_type |= TXGBE_MIRRCTL_POOL;\n+\t\tif (on) {\n+\t\t\tmp_lsb = mirror_conf->pool_mask & BIT_MASK32;\n+\t\t\tmp_msb = mirror_conf->pool_mask >> pool_mask_offset;\n+\t\t\tmr_conf->pool_mask = mirror_conf->pool_mask;\n+\t\t} else {\n+\t\t\tmp_lsb = 0;\n+\t\t\tmp_msb = 0;\n+\t\t\tmr_conf->pool_mask = 0;\n+\t\t}\n+\t}\n+\tif (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)\n+\t\tmirror_type |= TXGBE_MIRRCTL_UPLINK;\n+\tif (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)\n+\t\tmirror_type |= TXGBE_MIRRCTL_DNLINK;\n+\n+\t/* read mirror control register and recalculate it */\n+\tmr_ctl = rd32(hw, TXGBE_MIRRCTL(rule_id));\n+\n+\tif (on) {\n+\t\tmr_ctl |= mirror_type;\n+\t\tmr_ctl &= mirror_rule_mask;\n+\t\tmr_ctl |= mirror_conf->dst_pool << dst_pool_offset;\n+\t} else {\n+\t\tmr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);\n+\t}\n+\n+\tmr_conf->rule_type = mirror_conf->rule_type;\n+\tmr_conf->dst_pool = mirror_conf->dst_pool;\n+\n+\t/* write mirrror control register */\n+\twr32(hw, TXGBE_MIRRCTL(rule_id), mr_ctl);\n+\n+\t/* write pool mirrror control register */\n+\tif (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {\n+\t\twr32(hw, TXGBE_MIRRPOOLL(rule_id), mp_lsb);\n+\t\twr32(hw, TXGBE_MIRRPOOLH(rule_id + rule_mr_offset),\n+\t\t\t\tmp_msb);\n+\t}\n+\t/* write VLAN mirrror control register */\n+\tif (mirror_conf->rule_type & ETH_MIRROR_VLAN) {\n+\t\twr32(hw, TXGBE_MIRRVLANL(rule_id), mv_lsb);\n+\t\twr32(hw, TXGBE_MIRRVLANH(rule_id + rule_mr_offset),\n+\t\t\t\tmv_msb);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+txgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)\n+{\n+\tint mr_ctl = 0;\n+\tuint32_t lsb_val = 0;\n+\tuint32_t msb_val = 0;\n+\tconst uint8_t rule_mr_offset = 4;\n+\n+\tstruct txgbe_hw *hw = TXGBE_DEV_HW(dev);\n+\tstruct txgbe_mirror_info *mr_info = TXGBE_DEV_MR_INFO(dev);\n+\n+\tif (txgbe_vt_check(hw) < 0)\n+\t\treturn -ENOTSUP;\n+\n+\tif (rule_id >= TXGBE_MAX_MIRROR_RULES)\n+\t\treturn -EINVAL;\n+\n+\tmemset(&mr_info->mr_conf[rule_id], 0,\n+\t sizeof(struct rte_eth_mirror_conf));\n+\n+\t/* clear MIRRCTL register */\n+\twr32(hw, TXGBE_MIRRCTL(rule_id), mr_ctl);\n+\n+\t/* clear pool mask register */\n+\twr32(hw, TXGBE_MIRRPOOLL(rule_id), lsb_val);\n+\twr32(hw, TXGBE_MIRRPOOLH(rule_id + rule_mr_offset), msb_val);\n+\n+\t/* clear vlan mask register */\n+\twr32(hw, TXGBE_MIRRVLANL(rule_id), lsb_val);\n+\twr32(hw, TXGBE_MIRRVLANH(rule_id + rule_mr_offset), msb_val);\n+\n+\treturn 0;\n+}\n+\n static int\n txgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)\n {\n@@ -3725,6 +3909,8 @@ static const struct eth_dev_ops txgbe_eth_dev_ops = {\n \t.mac_addr_set = txgbe_set_default_mac_addr,\n \t.uc_hash_table_set = txgbe_uc_hash_table_set,\n \t.uc_all_hash_table_set = txgbe_uc_all_hash_table_set,\n+\t.mirror_rule_set = txgbe_mirror_rule_set,\n+\t.mirror_rule_reset = txgbe_mirror_rule_reset,\n \t.set_queue_rate_limit = txgbe_set_queue_rate_limit,\n \t.reta_update = txgbe_dev_rss_reta_update,\n \t.reta_query = txgbe_dev_rss_reta_query,\ndiff --git a/drivers/net/txgbe/txgbe_ethdev.h b/drivers/net/txgbe/txgbe_ethdev.h\nindex 99ca6aa9d..55f4b1213 100644\n--- a/drivers/net/txgbe/txgbe_ethdev.h\n+++ b/drivers/net/txgbe/txgbe_ethdev.h\n@@ -285,6 +285,7 @@ int txgbe_pf_host_configure(struct rte_eth_dev *eth_dev);\n \n uint32_t txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);\n \n+int txgbe_vt_check(struct txgbe_hw *hw);\n int txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,\n \t\t\t uint16_t tx_rate, uint64_t q_msk);\n int txgbe_set_queue_rate_limit(struct rte_eth_dev *dev, uint16_t queue_idx,\n", "prefixes": [ "v4", "53/58" ] }