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put:
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GET /api/patches/81135/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 81135,
    "url": "http://patches.dpdk.org/api/patches/81135/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20201016142742.87297-12-ciara.power@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20201016142742.87297-12-ciara.power@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20201016142742.87297-12-ciara.power@intel.com",
    "date": "2020-10-16T14:27:35",
    "name": "[v9,11/18] net/mlx5: add checks for max SIMD bitwidth",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "a8482605ec40c1296fd17b5ee6b17a1f8e481551",
    "submitter": {
        "id": 978,
        "url": "http://patches.dpdk.org/api/people/978/?format=api",
        "name": "Power, Ciara",
        "email": "ciara.power@intel.com"
    },
    "delegate": {
        "id": 24651,
        "url": "http://patches.dpdk.org/api/users/24651/?format=api",
        "username": "dmarchand",
        "first_name": "David",
        "last_name": "Marchand",
        "email": "david.marchand@redhat.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20201016142742.87297-12-ciara.power@intel.com/mbox/",
    "series": [
        {
            "id": 13067,
            "url": "http://patches.dpdk.org/api/series/13067/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=13067",
            "date": "2020-10-16T14:27:24",
            "name": "add max SIMD bitwidth to EAL",
            "version": 9,
            "mbox": "http://patches.dpdk.org/series/13067/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/81135/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/81135/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A82ACA04DB;\n\tFri, 16 Oct 2020 16:31:55 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id D2E181EF8A;\n\tFri, 16 Oct 2020 16:28:20 +0200 (CEST)",
            "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n by dpdk.org (Postfix) with ESMTP id 3B4491EF83\n for <dev@dpdk.org>; Fri, 16 Oct 2020 16:28:18 +0200 (CEST)",
            "from fmsmga003.fm.intel.com ([10.253.24.29])\n by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 16 Oct 2020 07:28:17 -0700",
            "from silpixa00400355.ir.intel.com (HELO\n silpixa00400355.ger.corp.intel.com) ([10.237.222.239])\n by FMSMGA003.fm.intel.com with ESMTP; 16 Oct 2020 07:28:14 -0700"
        ],
        "IronPort-SDR": [
            "\n MYEp1HNdIY0xnc4x7Y+gXBssJ5bk6SebOPsQZJtik305yciXYk/yKRxOCrsUKOay0sjN5xJZlH\n gmTeBI6LCO1A==",
            "\n aXg1hbaOYxRKVHMdfxRgan4XNGy3EnhahddJDqOnA17HSf+7KOQ7PkDhA7n00jtoQzuACbWEMt\n 0opq1BJ4uZug=="
        ],
        "X-IronPort-AV": [
            "E=McAfee;i=\"6000,8403,9775\"; a=\"163143023\"",
            "E=Sophos;i=\"5.77,383,1596524400\"; d=\"scan'208\";a=\"163143023\"",
            "E=Sophos;i=\"5.77,383,1596524400\"; d=\"scan'208\";a=\"357395074\""
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "From": "Ciara Power <ciara.power@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com,\n drc@linux.vnet.ibm.com, bruce.richardson@intel.com,\n konstantin.ananyev@intel.com, david.marchand@redhat.com,\n Ciara Power <ciara.power@intel.com>, Matan Azrad <matan@mellanox.com>,\n Shahaf Shuler <shahafs@mellanox.com>,\n Viacheslav Ovsiienko <viacheslavo@mellanox.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>,\n Matan Azrad <matan@nvidia.com>, Shahaf Shuler <shahafs@nvidia.com>",
        "Date": "Fri, 16 Oct 2020 15:27:35 +0100",
        "Message-Id": "<20201016142742.87297-12-ciara.power@intel.com>",
        "X-Mailer": "git-send-email 2.22.0",
        "In-Reply-To": "<20201016142742.87297-1-ciara.power@intel.com>",
        "References": "<20200807155859.63888-1-ciara.power@intel.com>\n <20201016142742.87297-1-ciara.power@intel.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Subject": "[dpdk-dev] [PATCH v9 11/18] net/mlx5: add checks for max SIMD\n\tbitwidth",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "When choosing a vector path to take, an extra condition must be\nsatisfied to ensure the max SIMD bitwidth allows for the CPU enabled\npath.\n\nCc: Matan Azrad <matan@mellanox.com>\nCc: Shahaf Shuler <shahafs@mellanox.com>\nCc: Viacheslav Ovsiienko <viacheslavo@mellanox.com>\n\nSigned-off-by: Ciara Power <ciara.power@intel.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n\n---\nv4: Updated enum name.\nv2: Moved check for max bitwidth into existing check vec\n    support function.\n---\n drivers/net/mlx5/mlx5_rxtx_vec.c | 2 ++\n 1 file changed, 2 insertions(+)",
    "diff": "diff --git a/drivers/net/mlx5/mlx5_rxtx_vec.c b/drivers/net/mlx5/mlx5_rxtx_vec.c\nindex 711dcd35fa..49f1b61ff8 100644\n--- a/drivers/net/mlx5/mlx5_rxtx_vec.c\n+++ b/drivers/net/mlx5/mlx5_rxtx_vec.c\n@@ -148,6 +148,8 @@ mlx5_check_vec_rx_support(struct rte_eth_dev *dev)\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tuint32_t i;\n \n+\tif (rte_get_max_simd_bitwidth() < RTE_SIMD_128)\n+\t\treturn -ENOTSUP;\n \tif (!priv->config.rx_vec_en)\n \t\treturn -ENOTSUP;\n \tif (mlx5_mprq_enabled(dev))\n",
    "prefixes": [
        "v9",
        "11/18"
    ]
}