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GET /api/patches/80962/?format=api
{ "id": 80962, "url": "http://patches.dpdk.org/api/patches/80962/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20201015152259.97562-19-ciara.power@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201015152259.97562-19-ciara.power@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201015152259.97562-19-ciara.power@intel.com", "date": "2020-10-15T15:22:59", "name": "[v7,18/18] acl: add checks for max SIMD bitwidth", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "70b31944d452e4284196dab836e68f0d53f7eea0", "submitter": { "id": 978, "url": "http://patches.dpdk.org/api/people/978/?format=api", "name": "Power, Ciara", "email": "ciara.power@intel.com" }, "delegate": { "id": 24651, "url": "http://patches.dpdk.org/api/users/24651/?format=api", "username": "dmarchand", "first_name": "David", "last_name": "Marchand", "email": "david.marchand@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20201015152259.97562-19-ciara.power@intel.com/mbox/", "series": [ { "id": 13019, "url": "http://patches.dpdk.org/api/series/13019/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=13019", "date": "2020-10-15T15:22:42", "name": "add max SIMD bitwidth to EAL", "version": 7, "mbox": "http://patches.dpdk.org/series/13019/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/80962/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/80962/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 88829A04DB;\n\tThu, 15 Oct 2020 17:30:39 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 99D4E1EB50;\n\tThu, 15 Oct 2020 17:24:31 +0200 (CEST)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n by dpdk.org (Postfix) with ESMTP id D128E1EB2A\n for <dev@dpdk.org>; Thu, 15 Oct 2020 17:24:27 +0200 (CEST)", "from fmsmga004.fm.intel.com ([10.253.24.48])\n by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 15 Oct 2020 08:24:26 -0700", "from silpixa00400355.ir.intel.com (HELO\n silpixa00400355.ger.corp.intel.com) ([10.237.222.239])\n by fmsmga004.fm.intel.com with ESMTP; 15 Oct 2020 08:24:23 -0700" ], "IronPort-SDR": [ "\n +uVZshg3/YR/e/yBT3mxy5YHBakvOYvjMKxbmeHplyuheyfUYoj064oz9rMKA8EjJmHVKtEpJA\n 5epor9fiYWZg==", "\n QEFX4Nl0msUtXOoY7YW2b5EkhZMfGkJX18hasLW7NQPGezFGn/g3kCrIIYHAoDYE4YcSXqCZuA\n ZyJFCJXdXkRw==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9775\"; a=\"162909291\"", "E=Sophos;i=\"5.77,379,1596524400\"; d=\"scan'208\";a=\"162909291\"", "E=Sophos;i=\"5.77,379,1596524400\"; d=\"scan'208\";a=\"346152215\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Ciara Power <ciara.power@intel.com>", "To": "dev@dpdk.org", "Cc": "viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com,\n drc@linux.vnet.ibm.com, bruce.richardson@intel.com,\n konstantin.ananyev@intel.com, david.marchand@redhat.com,\n Ciara Power <ciara.power@intel.com>", "Date": "Thu, 15 Oct 2020 16:22:59 +0100", "Message-Id": "<20201015152259.97562-19-ciara.power@intel.com>", "X-Mailer": "git-send-email 2.22.0", "In-Reply-To": "<20201015152259.97562-1-ciara.power@intel.com>", "References": "<20200807155859.63888-1-ciara.power@intel.com>\n <20201015152259.97562-1-ciara.power@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v7 18/18] acl: add checks for max SIMD bitwidth", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "When choosing a vector path to take, an extra condition must be\nsatisfied to ensure the max SIMD bitwidth allows for the CPU enabled\npath. These checks are added in the check alg helper functions.\n\nCc: Konstantin Ananyev <konstantin.ananyev@intel.com>\n\nSigned-off-by: Ciara Power <ciara.power@intel.com>\n\n---\nv7:\n - Removed global variable for max SIMD bitwidth.\n - Added helper function for checking AVX512 cpu flags.\n - Separated condition checking for the AVX512 algorithms to allow for\n checking 256/512 max SIMD bitwidth, respectively.\n - Added to docs to reflect the added changes in algorithm selection.\n---\n .../prog_guide/packet_classif_access_ctrl.rst | 14 ++++--\n lib/librte_acl/rte_acl.c | 48 ++++++++++++++-----\n lib/librte_acl/rte_acl.h | 1 +\n 3 files changed, 48 insertions(+), 15 deletions(-)", "diff": "diff --git a/doc/guides/prog_guide/packet_classif_access_ctrl.rst b/doc/guides/prog_guide/packet_classif_access_ctrl.rst\nindex 7659af8eb5..72c193b17f 100644\n--- a/doc/guides/prog_guide/packet_classif_access_ctrl.rst\n+++ b/doc/guides/prog_guide/packet_classif_access_ctrl.rst\n@@ -368,34 +368,40 @@ After rte_acl_build() over given AC context has finished successfully, it can be\n There are several implementations of classify algorithm:\n \n * **RTE_ACL_CLASSIFY_SCALAR**: generic implementation, doesn't require any specific HW support.\n+ Requires max SIMD bitwidth to be at least 64.\n \n * **RTE_ACL_CLASSIFY_SSE**: vector implementation, can process up to 8 flows in parallel. Requires SSE 4.1 support.\n+ Requires max SIMD bitwidth to be at least 128.\n \n * **RTE_ACL_CLASSIFY_AVX2**: vector implementation, can process up to 16 flows in parallel. Requires AVX2 support.\n+ Requires max SIMD bitwidth to be at least 256.\n \n * **RTE_ACL_CLASSIFY_NEON**: vector implementation, can process up to 8 flows\n- in parallel. Requires NEON support.\n+ in parallel. Requires NEON support. Requires max SIMD bitwidth to be at least 128.\n \n * **RTE_ACL_CLASSIFY_ALTIVEC**: vector implementation, can process up to 8\n- flows in parallel. Requires ALTIVEC support.\n+ flows in parallel. Requires ALTIVEC support. Requires max SIMD bitwidth to be at least 128.\n \n * **RTE_ACL_CLASSIFY_AVX512X16**: vector implementation, can process up to 16\n flows in parallel. Uses 256-bit width SIMD registers.\n- Requires AVX512 support.\n+ Requires AVX512 support. Requires max SIMD bitwidth to be at least 256.\n \n * **RTE_ACL_CLASSIFY_AVX512X32**: vector implementation, can process up to 32\n flows in parallel. Uses 512-bit width SIMD registers.\n- Requires AVX512 support.\n+ Requires AVX512 support. Requires max SIMD bitwidth to be at least 512.\n \n It is purely a runtime decision which method to choose, there is no build-time difference.\n All implementations operates over the same internal RT structures and use similar principles. The main difference is that vector implementations can manually exploit IA SIMD instructions and process several input data flows in parallel.\n At startup ACL library determines the highest available classify method for the given platform and sets it as default one. Though the user has an ability to override the default classifier function for a given ACL context or perform particular search using non-default classify method. In that case it is user responsibility to make sure that given platform supports selected classify implementation.\n+The max SIMD bitwidth value set in EAL is also taken into consideration when determining if a classify method is supported, see :ref:`max_simd_bitwidth` for more information.\n \n .. note::\n \n Right now ``RTE_ACL_CLASSIFY_AVX512X32`` is not selected by default\n (due to possible frequency level change), but it can be selected at\n runtime by apps through the use of ACL API: ``rte_acl_set_ctx_classify``.\n+ The max SIMD bitwidth value will also need to be set to 512 to enable this classify method.\n+ See :doc:`../howto/avx512` for more information about setting this value.\n \n Application Programming Interface (API) Usage\n ---------------------------------------------\ndiff --git a/lib/librte_acl/rte_acl.c b/lib/librte_acl/rte_acl.c\nindex 7c2f60b2d6..026d2e7430 100644\n--- a/lib/librte_acl/rte_acl.c\n+++ b/lib/librte_acl/rte_acl.c\n@@ -114,9 +114,13 @@ acl_check_alg_arm(enum rte_acl_classify_alg alg)\n {\n \tif (alg == RTE_ACL_CLASSIFY_NEON) {\n #if defined(RTE_ARCH_ARM64)\n-\t\treturn 0;\n+\t\tif (rte_get_max_simd_bitwidth() >= RTE_SIMD_128)\n+\t\t\treturn 0;\n+\t\telse\n+\t\t\treturn -ENOTSUP;\n #elif defined(RTE_ARCH_ARM)\n-\t\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_NEON))\n+\t\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_NEON) &&\n+\t\t\t\trte_get_max_simd_bitwidth() >= RTE_SIMD_128)\n \t\t\treturn 0;\n \t\treturn -ENOTSUP;\n #else\n@@ -136,7 +140,10 @@ acl_check_alg_ppc(enum rte_acl_classify_alg alg)\n {\n \tif (alg == RTE_ACL_CLASSIFY_ALTIVEC) {\n #if defined(RTE_ARCH_PPC_64)\n-\t\treturn 0;\n+\t\tif (rte_get_max_simd_bitwidth() >= RTE_SIMD_128)\n+\t\t\treturn 0;\n+\t\telse\n+\t\t\treturn -ENOTSUP;\n #else\n \t\treturn -ENOTSUP;\n #endif\n@@ -145,6 +152,17 @@ acl_check_alg_ppc(enum rte_acl_classify_alg alg)\n \treturn -EINVAL;\n }\n \n+#ifdef CC_AVX512_SUPPORT\n+static int\n+acl_check_avx512_cpu_flags(void)\n+{\n+\treturn (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) &&\n+\t\t\trte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512VL) &&\n+\t\t\trte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512CD) &&\n+\t\t\trte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW));\n+}\n+#endif\n+\n /*\n * Helper function for acl_check_alg.\n * Check support for x86 specific classify methods.\n@@ -152,13 +170,19 @@ acl_check_alg_ppc(enum rte_acl_classify_alg alg)\n static int\n acl_check_alg_x86(enum rte_acl_classify_alg alg)\n {\n-\tif (alg == RTE_ACL_CLASSIFY_AVX512X16 ||\n-\t\t\talg == RTE_ACL_CLASSIFY_AVX512X32) {\n+\tif (alg == RTE_ACL_CLASSIFY_AVX512X32) {\n #ifdef CC_AVX512_SUPPORT\n-\t\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) &&\n-\t\t\trte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512VL) &&\n-\t\t\trte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512CD) &&\n-\t\t\trte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW))\n+\t\tif (acl_check_avx512_cpu_flags() != 0 &&\n+\t\t\trte_get_max_simd_bitwidth() >= RTE_SIMD_512)\n+\t\t\treturn 0;\n+#endif\n+\t\treturn -ENOTSUP;\n+\t}\n+\n+\tif (alg == RTE_ACL_CLASSIFY_AVX512X16) {\n+#ifdef CC_AVX512_SUPPORT\n+\t\tif (acl_check_avx512_cpu_flags() != 0 &&\n+\t\t\trte_get_max_simd_bitwidth() >= RTE_SIMD_256)\n \t\t\treturn 0;\n #endif\n \t\treturn -ENOTSUP;\n@@ -166,7 +190,8 @@ acl_check_alg_x86(enum rte_acl_classify_alg alg)\n \n \tif (alg == RTE_ACL_CLASSIFY_AVX2) {\n #ifdef CC_AVX2_SUPPORT\n-\t\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))\n+\t\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) &&\n+\t\t\t\trte_get_max_simd_bitwidth() >= RTE_SIMD_256)\n \t\t\treturn 0;\n #endif\n \t\treturn -ENOTSUP;\n@@ -174,7 +199,8 @@ acl_check_alg_x86(enum rte_acl_classify_alg alg)\n \n \tif (alg == RTE_ACL_CLASSIFY_SSE) {\n #ifdef RTE_ARCH_X86\n-\t\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1))\n+\t\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1) &&\n+\t\t\t\trte_get_max_simd_bitwidth() >= RTE_SIMD_128)\n \t\t\treturn 0;\n #endif\n \t\treturn -ENOTSUP;\ndiff --git a/lib/librte_acl/rte_acl.h b/lib/librte_acl/rte_acl.h\nindex 1bfed00743..f7f5f08701 100644\n--- a/lib/librte_acl/rte_acl.h\n+++ b/lib/librte_acl/rte_acl.h\n@@ -329,6 +329,7 @@ rte_acl_classify_alg(const struct rte_acl_ctx *ctx,\n * New default classify algorithm for given ACL context.\n * It is the caller responsibility to ensure that the value refers to the\n * existing algorithm, and that it could be run on the given CPU.\n+ * The max SIMD bitwidth value in EAL must also allow for the chosen algorithm.\n * @return\n * - -EINVAL if the parameters are invalid.\n * - -ENOTSUP requested algorithm is not supported by given platform.\n", "prefixes": [ "v7", "18/18" ] }