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GET /api/patches/80954/?format=api
{ "id": 80954, "url": "http://patches.dpdk.org/api/patches/80954/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20201015152259.97562-11-ciara.power@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201015152259.97562-11-ciara.power@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201015152259.97562-11-ciara.power@intel.com", "date": "2020-10-15T15:22:51", "name": "[v7,10/18] net/ixgbe: add checks for max SIMD bitwidth", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "8bd0706b6ea302af7cd766819be469fedaecff51", "submitter": { "id": 978, "url": "http://patches.dpdk.org/api/people/978/?format=api", "name": "Power, Ciara", "email": "ciara.power@intel.com" }, "delegate": { "id": 24651, "url": "http://patches.dpdk.org/api/users/24651/?format=api", "username": "dmarchand", "first_name": "David", "last_name": "Marchand", "email": "david.marchand@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20201015152259.97562-11-ciara.power@intel.com/mbox/", "series": [ { "id": 13019, "url": "http://patches.dpdk.org/api/series/13019/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=13019", "date": "2020-10-15T15:22:42", "name": "add max SIMD bitwidth to EAL", "version": 7, "mbox": "http://patches.dpdk.org/series/13019/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/80954/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/80954/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id CD56CA04DB;\n\tThu, 15 Oct 2020 17:27:25 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 006A01EAE5;\n\tThu, 15 Oct 2020 17:23:58 +0200 (CEST)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n by dpdk.org (Postfix) with ESMTP id 15F3E1EAD5\n for <dev@dpdk.org>; Thu, 15 Oct 2020 17:23:55 +0200 (CEST)", "from fmsmga004.fm.intel.com ([10.253.24.48])\n by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 15 Oct 2020 08:23:55 -0700", "from silpixa00400355.ir.intel.com (HELO\n silpixa00400355.ger.corp.intel.com) ([10.237.222.239])\n by fmsmga004.fm.intel.com with ESMTP; 15 Oct 2020 08:23:51 -0700" ], "IronPort-SDR": [ "\n NbUW7o/qFO6NnxSeouZCOrLfUR6ePT9CFWMSHrJppjvCEwtjp6Js6jP5xWdluzb3kAcWe/2t1F\n +bwl3fTLyPCw==", "\n n8V0sbcQHuGOtoofuhzZVtIGBw7TJCzvx56b7IIseC11BFoRt6RjhLTUiGSyziC7VqFYqBQ4Vt\n LdRTlczTlBpQ==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9775\"; a=\"162909192\"", "E=Sophos;i=\"5.77,379,1596524400\"; d=\"scan'208\";a=\"162909192\"", "E=Sophos;i=\"5.77,379,1596524400\"; d=\"scan'208\";a=\"346151921\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Ciara Power <ciara.power@intel.com>", "To": "dev@dpdk.org", "Cc": "viktorin@rehivetech.com, ruifeng.wang@arm.com, jerinj@marvell.com,\n drc@linux.vnet.ibm.com, bruce.richardson@intel.com,\n konstantin.ananyev@intel.com, david.marchand@redhat.com,\n Ciara Power <ciara.power@intel.com>, Wei Zhao <wei.zhao1@intel.com>,\n Jeff Guo <jia.guo@intel.com>, Haiyue Wang <haiyue.wang@intel.com>", "Date": "Thu, 15 Oct 2020 16:22:51 +0100", "Message-Id": "<20201015152259.97562-11-ciara.power@intel.com>", "X-Mailer": "git-send-email 2.22.0", "In-Reply-To": "<20201015152259.97562-1-ciara.power@intel.com>", "References": "<20200807155859.63888-1-ciara.power@intel.com>\n <20201015152259.97562-1-ciara.power@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v7 10/18] net/ixgbe: add checks for max SIMD\n\tbitwidth", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "When choosing a vector path to take, an extra condition must be\nsatisfied to ensure the max SIMD bitwidth allows for the CPU enabled\npath.\n\nCc: Wei Zhao <wei.zhao1@intel.com>\nCc: Jeff Guo <jia.guo@intel.com>\n\nSigned-off-by: Ciara Power <ciara.power@intel.com>\nAcked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>\nReviewed-by: Haiyue Wang <haiyue.wang@intel.com>\n\n---\nv4:\n - Updated enum name.\n - Moved placement of condition check.\n - Added condition check to tx cleanup path selection.\n---\n drivers/net/ixgbe/ixgbe_rxtx.c | 5 ++++-\n 1 file changed, 4 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c\nindex 29d385c062..3141398e10 100644\n--- a/drivers/net/ixgbe/ixgbe_rxtx.c\n+++ b/drivers/net/ixgbe/ixgbe_rxtx.c\n@@ -2405,6 +2405,7 @@ ixgbe_dev_tx_done_cleanup(void *tx_queue, uint32_t free_cnt)\n #endif\n \t\t\ttxq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST) {\n \t\tif (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&\n+\t\t\t\trte_get_max_simd_bitwidth() >= RTE_SIMD_128 &&\n \t\t\t\t(rte_eal_process_type() != RTE_PROC_PRIMARY ||\n \t\t\t\t\ttxq->sw_ring_v != NULL)) {\n \t\t\treturn ixgbe_tx_done_cleanup_vec(txq, free_cnt);\n@@ -2503,6 +2504,7 @@ ixgbe_set_tx_function(struct rte_eth_dev *dev, struct ixgbe_tx_queue *txq)\n \t\tPMD_INIT_LOG(DEBUG, \"Using simple tx code path\");\n \t\tdev->tx_pkt_prepare = NULL;\n \t\tif (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&\n+\t\t\t\trte_get_max_simd_bitwidth() >= RTE_SIMD_128 &&\n \t\t\t\t(rte_eal_process_type() != RTE_PROC_PRIMARY ||\n \t\t\t\t\tixgbe_txq_vec_setup(txq) == 0)) {\n \t\t\tPMD_INIT_LOG(DEBUG, \"Vector tx enabled.\");\n@@ -4744,7 +4746,8 @@ ixgbe_set_rx_function(struct rte_eth_dev *dev)\n \t * conditions to be met and Rx Bulk Allocation should be allowed.\n \t */\n \tif (ixgbe_rx_vec_dev_conf_condition_check(dev) ||\n-\t !adapter->rx_bulk_alloc_allowed) {\n+\t !adapter->rx_bulk_alloc_allowed ||\n+\t\t\trte_get_max_simd_bitwidth() < RTE_SIMD_128) {\n \t\tPMD_INIT_LOG(DEBUG, \"Port[%d] doesn't meet Vector Rx \"\n \t\t\t\t \"preconditions\",\n \t\t\t dev->data->port_id);\n", "prefixes": [ "v7", "10/18" ] }