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GET /api/patches/80103/?format=api
{ "id": 80103, "url": "http://patches.dpdk.org/api/patches/80103/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20201009061142.305-1-lizh@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201009061142.305-1-lizh@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201009061142.305-1-lizh@nvidia.com", "date": "2020-10-09T06:11:42", "name": "[v9,1/1] net/mlx5: support match ICMP identifier fields", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "5c46106d11df96b649e38fd774f8fdf9b5c8cf8a", "submitter": { "id": 1967, "url": "http://patches.dpdk.org/api/people/1967/?format=api", "name": "Li Zhang", "email": "lizh@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20201009061142.305-1-lizh@nvidia.com/mbox/", "series": [ { "id": 12808, "url": "http://patches.dpdk.org/api/series/12808/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12808", "date": "2020-10-09T06:11:42", "name": "[v9,1/1] net/mlx5: support match ICMP identifier fields", "version": 9, "mbox": "http://patches.dpdk.org/series/12808/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/80103/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/80103/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 42CDBA04BC;\n\tFri, 9 Oct 2020 08:11:52 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 852BD1BCDB;\n\tFri, 9 Oct 2020 08:11:50 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id AEF031BEDC\n for <dev@dpdk.org>; Fri, 9 Oct 2020 08:11:49 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n lizh@nvidia.com)\n with SMTP; 9 Oct 2020 09:11:44 +0300", "from nvidia.com (c-141-86-1-005.mtl.labs.mlnx [10.141.86.5])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0996BiM3012017;\n Fri, 9 Oct 2020 09:11:44 +0300" ], "From": "Li Zhang <lizh@nvidia.com>", "To": "dekelp@nvidia.com, orika@nvidia.com, viacheslavo@nvidia.com,\n matan@nvidia.com", "Cc": "dev@dpdk.org, thomas@monjalon.net, rasland@nvidia.com", "Date": "Fri, 9 Oct 2020 09:11:42 +0300", "Message-Id": "<20201009061142.305-1-lizh@nvidia.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20201009060600.32561-1-lizh@nvidia.com>", "References": "<20201009060600.32561-1-lizh@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v9 1/1] net/mlx5: support match ICMP identifier\n\tfields", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "PRM expose fields \"Icmp_header_data\" in IPv4 ICMP.\nUpdate ICMP mask parameter with ICMP identifier and sequence number fields.\nICMP sequence number spec with mask, Icmp_header_data low 16 bits are set.\nICMP identifier spec with mask, Icmp_header_data high 16 bits are set.\n\nSigned-off-by: Li Zhang <lizh@nvidia.com>\nAcked-by: Ori Kam <orika@nvidia.com>\n---\n doc/guides/nics/mlx5.rst | 4 ++--\n doc/guides/rel_notes/release_20_11.rst | 2 +-\n drivers/net/mlx5/mlx5_flow.c | 10 ++++++++--\n drivers/net/mlx5/mlx5_flow_dv.c | 13 +++++++++++++\n 4 files changed, 24 insertions(+), 5 deletions(-)", "diff": "diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst\nindex b0614ae335..a174cdd5f5 100644\n--- a/doc/guides/nics/mlx5.rst\n+++ b/doc/guides/nics/mlx5.rst\n@@ -288,7 +288,7 @@ Limitations\n - The input buffer, providing the removal size, is not validated.\n - The buffer size must match the length of the headers to be removed.\n \n-- ICMP/ICMP6 code/type matching, IP-in-IP and MPLS flow matching are all\n+- ICMP(code/type/identifier/sequence number) / ICMP6(code/type) matching, IP-in-IP and MPLS flow matching are all\n mutually exclusive features which cannot be supported together\n (see :ref:`mlx5_firmware_config`).\n \n@@ -1009,7 +1009,7 @@ Below are some firmware configurations listed.\n \n FLEX_PARSER_PROFILE_ENABLE=1\n \n-- enable ICMP/ICMP6 code/type fields matching::\n+- enable ICMP(code/type/identifier/sequence number) / ICMP6(code/type) fields matching::\n \n FLEX_PARSER_PROFILE_ENABLE=2\n \ndiff --git a/doc/guides/rel_notes/release_20_11.rst b/doc/guides/rel_notes/release_20_11.rst\nindex b0637640d1..e22e0c3981 100644\n--- a/doc/guides/rel_notes/release_20_11.rst\n+++ b/doc/guides/rel_notes/release_20_11.rst\n@@ -102,7 +102,7 @@ New Features\n * Added flag action.\n * Added raw encap/decap actions.\n * Added VXLAN encap/decap actions.\n- * Added ICMP and ICMP6 matching items.\n+ * Added ICMP(code/type/identifier/sequence number) and ICMP6(code/type) matching items.\n * Added option to set port mask for insertion/deletion:\n ``--portmask=N``\n where N represents the hexadecimal bitmask of ports used.\ndiff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex 691eb9a3cd..0a54818c0c 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -1629,6 +1629,12 @@ mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,\n \t\t\t struct rte_flow_error *error)\n {\n \tconst struct rte_flow_item_icmp *mask = item->mask;\n+\tconst struct rte_flow_item_icmp nic_mask = {\n+\t\t.hdr.icmp_type = 0xff,\n+\t\t.hdr.icmp_code = 0xff,\n+\t\t.hdr.icmp_ident = RTE_BE16(0xffff),\n+\t\t.hdr.icmp_seq_nb = RTE_BE16(0xffff),\n+\t};\n \tconst int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);\n \tconst uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :\n \t\t\t\t MLX5_FLOW_LAYER_OUTER_L3_IPV4;\n@@ -1651,10 +1657,10 @@ mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, item,\n \t\t\t\t\t \"multiple L4 layers not supported\");\n \tif (!mask)\n-\t\tmask = &rte_flow_item_icmp_mask;\n+\t\tmask = &nic_mask;\n \tret = mlx5_flow_item_acceptable\n \t\t(item, (const uint8_t *)mask,\n-\t\t (const uint8_t *)&rte_flow_item_icmp_mask,\n+\t\t (const uint8_t *)&nic_mask,\n \t\t sizeof(struct rte_flow_item_icmp), error);\n \tif (ret < 0)\n \t\treturn ret;\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 79fdf34c0e..2bbfcea1ed 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -7378,6 +7378,8 @@ flow_dv_translate_item_icmp(void *matcher, void *key,\n {\n \tconst struct rte_flow_item_icmp *icmp_m = item->mask;\n \tconst struct rte_flow_item_icmp *icmp_v = item->spec;\n+\tuint32_t icmp_header_data_m = 0;\n+\tuint32_t icmp_header_data_v = 0;\n \tvoid *headers_m;\n \tvoid *headers_v;\n \tvoid *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,\n@@ -7412,6 +7414,17 @@ flow_dv_translate_item_icmp(void *matcher, void *key,\n \t\t icmp_m->hdr.icmp_code);\n \tMLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,\n \t\t icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);\n+\ticmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);\n+\ticmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;\n+\tif (icmp_header_data_m) {\n+\t\ticmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);\n+\t\ticmp_header_data_v |=\n+\t\t\t rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;\n+\t\tMLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,\n+\t\t\t icmp_header_data_m);\n+\t\tMLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,\n+\t\t\t icmp_header_data_v & icmp_header_data_m);\n+\t}\n }\n \n /**\n", "prefixes": [ "v9", "1/1" ] }